SY89827LHG TR Micrel Inc, SY89827LHG TR Datasheet - Page 4

• Manufacturer Part Number: SY89827LHG TR
• Manufacturer: Micrel Inc
• Type: Clock Driverr

Specifications of SY89827LHG TR

• Number Of Clock Inputs: 4
• Mode Of Operation: Differential
• Output Frequency: 500MHz
• Output Logic Level: HSTL
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.47V
• Package Type: TQFP EP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: HSTL/LVPECL
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Micrel, Inc.
M9999-073010
[e-mail] or [phone]
40, 41, 48, 49, 64
63, 61, 59, 57, 55
53, 51, 47, 45, 43
62, 60, 58, 56, 54
52, 50, 46, 44, 42
39, 37, 35, 31, 29
27, 25, 23, 21, 19
38, 36, 34, 30, 28
26, 24, 22, 20, 18
PIN DESCRIPTIONS
Pin Number
17, 32, 33,
12, 13
5, 6
2, 3
8, 9
14
16
11
15
10
7
1
4
/LVPECL_CLKB
/LVPECL_CLKA
LVPECL_CLKB
LVPECL_CLKA
/HSTL_CLKB
/HSTL_CLKA
HSTL_CLKB
HSTL_CLKA
/Q10 – /Q19
CLK_SEL1
CLK_SEL2
Q10 – Q19
Pin Name
/Q0 – /Q9
Q0 – Q9
VCCO
SEL1
SEL2
VCCI
GND
OE1
OE2
Output
Output
Output
Output
Power
Power
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
LVPECL
LVPECL
LVTTL/
LVTTL/
LVTTL/
LVTTL/
LVTTL/
LVTTL/
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
Type
pull-down Can be left floating. Floating input, if selected produces a LOW
pull-down
Internal
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
75kΩ
75kΩ
11kΩ
11kΩ
11kΩ
11kΩ
11kΩ
11kΩ
P/U
4
Pin Function
Differential clock input selected by CLK_SEL1, SEL1 and SEL2.
Can be left floating if not selected. Floating input, if selected
produces an indeterminate output. HSTL input signal requires
external termination 50Ω-to-GND.
Differential clock input selected by CLK_SEL1, SEL1 and SEL2.
Can be left floating if not selected. Floating input, if selected
produces an indeterminate output. HSTL input signal requires
external termination 50Ω-to-GND.
Differential clock input selected by CLK_SEL1, SEL1 and SEL2.
at output. Requires external termination. See Figure 1.
Differential clock input selected by CLK_SEL2, SEL1 and SEL2.
Requires external termination. See Figure 1.
Selects HSTL_CLKA input when LOW and LVPECL_CLKA
input when HIGH.
Selects HSTL_CLKB input when LOW and LVPECL_CLKB
input when HIGH.
Selects input source CLKA when LOW and CLKB
when HIGH for outputs Q0 – Q9 and /Q0 – /Q9.
Selects input source CLKA when LOW and CLKB
when HIGH for outputs Q10 – Q19 and /Q10 – /Q19.
Enable input synchronized internally to prevent glitching of the
Q0 – Q9 and /Q0 – /Q9 outputs.
Enable input synchronized internally to prevent glitching of the
Q10 – Q19 and /Q10 – /Q19 outputs.
Core VCC connected to 3.3V supply. Bypass with 0.1µF in
parallel with 0.01µF low ESR capacitors as close to VCC pins as
possible.
Output buffer VCC connected to 1.8V nominal supply. All VCCO
pins should be connected together on the PCB. Bypass with
0.1µF in parallel with 0.01µF low ESR capacitors as close to
VCCO pins as possible.
Ground.
Differential clock outputs from CLKA when SEL1 = LOW and
from CLKB when SEL1 = HIGH. HSTL outputs (Q and /Q) must
be terminated with 50Ω-to-GND. Q outputs are static when
OE1 = LOW. Unused output pairs may be left floating.
Differential clock outputs (complement) from CLKA when SEL1 =
LOW and from CLKB when SEL1 = HIGH. HSTL outputs (Q and
/Q) must be terminated with 50Ω-to-GND. /Q outputs are static
HIGH when OE1 = LOW. Unused output pairs may be left
floating.
Differential outputs from CLKA when SEL2 = LOW and from
CLKB when SEL2 = HIGH. HSTL outputs (Q and /Q) must be
terminated with 50Ω-to-GND. Q outputs are static LOW when
OE2 = LOW. Unused output pairs may be left floating.
Differential outputs (complement) from CLKA when SEL2 = LOW
and from CLKB when SEL2 = HIGH. HSTL outputs (Q and /Q)
must be terminated with 50Ω-to-GND. /Q outputs are static HIGH
when OE2 = LOW. Unused output pairs may be left floating.
Precision Edge
SY89827L
®