MC100ES6221TB IDT, Integrated Device Technology Inc, MC100ES6221TB Datasheet - Page 8

• Manufacturer Part Number: MC100ES6221TB
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of MC100ES6221TB

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 2000MHz
• Output Logic Level: ECL/PECL
• Operating Supply Voltage (min): -2.375/2.375V
• Operating Supply Voltage (typ): -2.5/-3.3/2.5/3.3V
• Operating Supply Voltage (max): -3.465/3.465V
• Package Type: TQFP EP
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Signal Type: ECL/HSTL/PECL
• Mounting: Surface Mount
• Pin Count: 52
• Quiescent Current: 160mA
• Lead Free Status / RoHS Status: Not Compliant

IDT™ Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES6221
Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer
8
Understanding the Junction Temperature Range of the
MC100ES6221
skew capabilities of the MC100ES6221, the MC100ES6221
is specified, characterized and tested for the junction
temperature range of T
thermal performance depends on the PCB type, design,
thermal management and natural or forced air convection,
the junction temperature provides an exact way to correlate
the application specific conditions to the published
performance data of this data sheet. The correlation of the
junction temperature range to the application ambient
temperature range and vice versa can be done by
calculation:
17°C/W (2s2p board, 200 ft/min airflow, see
typical power consumption of 1148 mW (all outputs
terminated 50 ohms to V
independent), the junction temperature of the MC100ES6221
is approximately T
temperature in this example case calculates to
maximum ambient temperature is 89°C. See
Exceeding the minimum junction temperature specification of
the MC100ES6221 does not have a significant impact on the
device functionality. However, the continuous use the
MC100ES6221 at high ambient temperatures requires
thermal management to not exceed the specified maximum
junction temperature. Please see the application note
AN1545 for a power consumption calculation guideline.
Table 8. Ambient Temperature Ranges (P
MC100ES6221
1. The MC100ES6221 device function is guaranteed from
Natural convection
To make the optimum use of high clock frequency and low
Assuming a thermal resistance (junction to ambient) of
T
A
100 ft/min
200 ft/min
400 ft/min
800 ft/min
= –40°C to T
R
thja
(2s2p board)
J
A
= 110°C
+ 21°C, and the minimum ambient
T
J
J
= T
= 0°C to +110°C. Because the exact
20°C/W
18°C/W
17°C/W
16°C/W
15°C/W
TT
A
, V
+ R
CC
thja
= 3.3 V, frequency
⋅ P
T
tot
–23 °C
–21 °C
–20 °C
–18 °C
–17 °C
A, min
(1)
tot
Table
APPLICATIONS INFORMATION
Table
= 1148 mW)
–
21°C (the
8) and a
T
8).
87°C
89°C
90°C
92°C
93°C
A, max
8
Maintaining Lowest Device Skew
skew of 50 ps and a part-to-part skew of max. 270 ps. To
ensure low skew clock signals in the application, both outputs
of any differential output pair need to be terminated
identically, even if only one output is used. When fewer than
all nine output pairs are used, identical termination of all
output pairs within the output bank is recommended. This will
reduce the device power consumption while maintaining
minimum output skew.
Power Supply Bypassing
differential architecture of the MC100ES6221 supports low
noise signal operation at high frequencies. In order to
maintain its superior signal quality, all V
bypassed by high-frequency ceramic capacitors connected
to GND. If the spectral frequencies of the internally generated
switching noise on the supply pins cross the series resonant
point of an individual bypass capacitor, its overall impedance
begins to look inductive and thus increases with increasing
frequency. The parallel capacitor combination shown ensures
that a low impedance path to ground exists for frequencies
well above the noise bandwidth.
The MC100ES6221 guarantees low output-to-output bank
The MC100ES6221 is a mixed analog/digital product. The
V
CC
Figure 5. V
33...100 nF
CC
Power Supply Bypass
Advanced Clock Drivers Devices
0.1 nF
Freescale Semiconductor
CC
V
pins should be
MC100ES6221
CC
MC100ES6221
NETCOM