ICS8533AGI-31 IDT, Integrated Device Technology Inc, ICS8533AGI-31 Datasheet - Page 9

• Manufacturer Part Number: ICS8533AGI-31
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS8533AGI-31

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 650MHz
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
V
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
Figure 3A. HiPerClockS CLK/nCLK Input
Figure 3C. HiPerClockS CLK/nCLK Input
Figure 3E. HiPerClockS CLK/nCLK Input
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
PP
ICS8533I-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
and V
2.5V
1.8V
3.3V
HCSL
LVPECL
CMR
*Optional – R3 and R4 can be 0Ω
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Driven by a 3.3V LVPECL Driver
Driven by a 3.3V HCSL Driver
input requirements. Figures 3A to 3F show interface
*R3
*R4
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
33
33
Zo = 50Ω
Zo = 50Ω
R3
125
R1
50
3.3V
SWING
R1
84
R1
50
R2
50
R4
125
R2
84
and V
R2
50
CLK
nCLK
CLK
nCLK
OH
CLK
nCLK
3.3V
3.3V
must meet the
3.3V
HiPerClockS
Input
HiPerClockS
Input
HiPerClockS
Input
9
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
Figure 3B. HiPerClockS CLK/nCLK Input
Figure 3D. HiPerClockS CLK/nCLK Input
Figure 3F. HiPerClockS CLK/nCLK Input
2.5V
3.3V
3.3V
SSTL
LVDS
LVPECL
Driven by a 3.3V LVPECL Driver
Driven by a 3.3V LVDS Driver
Driven by a 2.5V SSTL Driver
Zo = 60Ω
Zo = 60Ω
Zo = 50Ω
Zo = 50Ω
ICS8533AGI-31 REV. A DECEMBER 13, 2007
Zo = 50Ω
Zo = 50Ω
R3
120
2.5V
R1
120
R1
50
R2
50
R4
120
R2
120
R2
50
R1
100
CLK
nCLK
PRELIMINARY
CLK
nCLK
CLK
nCLK
3.3V
3.3V
HiPerClockS
3.3V
HiPerClockS
Input
Receiver