ICS83948AYI IDT, Integrated Device Technology Inc, ICS83948AYI Datasheet - Page 8

• Manufacturer Part Number: ICS83948AYI
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS83948AYI

• Number Of Clock Inputs: 2
• Output Frequency: 250MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Package Type: LQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the V
V
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
Figure 2A. HiPerClockS CLK/nCLK Input
Figure 2C. HiPerClockS CLK/nCLK Input
Figure 2E. HiPerClockS CLK/nCLK Input
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
CMR
ICS83948I
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
2.5V
input requirements. Figures 2A to 2F show interface
1.8V
3.3V
HCSL
LVPECL
*Optional – R3 and R4 can be 0Ω
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Driven by a 3.3V LVPECL Driver
Driven by a 3.3V HCSL Driver
*R3
*R4
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
33
33
Zo = 50Ω
Zo = 50Ω
R3
125
R1
50
3.3V
R1
84
R1
50
R4
125
R2
50
R2
84
R2
50
CLK
nCLK
CLK
nCLK
CLK
nCLK
3.3V
3.3V
3.3V
HiPerClockS
Input
HiPerClockS
Input
HiPerClockS
Input
PP
and
8
component to confirm the driver termination requirements. For
example, in Figure 2A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
Figure 2B. HiPerClockS CLK/nCLK Input
Figure 2D. HiPerClockS CLK/nCLK Input
Figure 2F. HiPerClockS CLK/nCLK Input
2.5V
3.3V
3.3V
SSTL
LVDS
LVPECL
Driven by a 3.3V LVPECL Driver
Driven by a 3.3V LVDS Driver
Driven by a 2.5V SSTL Driver
Zo = 60Ω
Zo = 60Ω
Zo = 50Ω
Zo = 50Ω
ICS83948AYI REV. C NOVEMBER 7, 2008
Zo = 50Ω
Zo = 50Ω
R3
120
2.5V
R1
120
R1
50
R2
50
R4
120
R2
120
R2
50
R1
100
CLK
nCLK
CLK
nCLK
CLK
nCLK
3.3V
3.3V
HiPerClockS
3.3V
HiPerClockS
Input
Receiver