ICS870S208BK IDT, Integrated Device Technology Inc, ICS870S208BK Datasheet - Page 2

• Manufacturer Part Number: ICS870S208BK
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of ICS870S208BK

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 250MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

T
The ICS87S0208 has a glitch free input mux that is controlled
by the CLK_SEL pin. It is designed to switch between 2 input
clocks whether running or not.
are running, when CLK_SEL changes, the output clocks go
When DIV_SEL changes, the part waits for the output to
complete the cycle of the selected divider then changes
seamlessly to the new divider.
When an Output Enable pin is pulled low, the part waits for the
output to complete its period, then transitions to a Hi-Z state.
When Output Enable is asserted, the output transitions from the
IDT
F
WO
ICS870S208
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
UNTIONAL
™
/ ICS
V
ALID
™
LVCMOS FANOUT BUFFER W/DIVIDER
C
LOCKS
DIV_SEL
CLK_SEL
CLK ÷ 1
CLK ÷ 2
D
Output
Output
CLK1
Output
CLK0
CLK1
ESCRIPTION
OE
In the case where both clocks
F
F
IGURE
IGURE
F
IGURE
1B. DIV_SEL
1A. CLK_SEL T
1C. OE
2
low after one cycle of the output clock (nominally). The outputs
then stay low for one cycle of the new input clock (nominally)
and then begin to follow the new input clock. This is shown in
Figure 1A.
Hi-Z to a low state to ensure a clean rising edge of the first output
clock.
X
T
IMING
X
T
IMING
IMING
D
IAGRAM
D
D
IAGRAM
IAGRAM
ICS870S208BK REV. A NOVEMBER 9, 2007
PRELIMINARY