ICS870S208BK IDT, Integrated Device Technology Inc, ICS870S208BK Datasheet - Page 3

• Manufacturer Part Number: ICS870S208BK
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of ICS870S208BK

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 250MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

IDT
If the selected input clock goes bad (stuck high or low for over
approximately 200ns), an internal input bad flag is set. When the
input bad flag is set, the output goes low until the next valid clock
If the input bad flag has been set (The input has been stuck
high or low for over approximately 200ns), and OEx is pulled
low, the output will immediately go to a HighZ state. If the clock
B
An internal timer monitors the state of both input clocks. If a
clock is stopped (stuck high or low for over approximately
200ns), its internal input bad flag is set and the part will perform
as depicted in the following diagrams. If the clock is restored,
the internal input bad detector waits for 4 full clock periods
before clearing the input bad flag and returning to normal
operation.
ICS870S208
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
AD
™
/ ICS
I
NPUT
™
LVCMOS FANOUT BUFFER W/DIVIDER
C
LOCK
CLK_SEL
Output
DIV_SEL
Output
CLK
CLK÷2
Output
CLK0
CLK1
OE
CLK
Detect, 200ns
Input Bad
Detect, 200ns
Detect, 200ns
Input Bad
Input Bad
F
F
IGURE
IGURE
F
IGURE
1D. CLK_SEL
1E. DIV_SEL
1F. OE
X WITH
X WITH
3
WITH
B
If the selected input clock goes bad (stuck high or low for over
approximately 200ns), an internal input bad flag is set. When the
input bad flag is set, the output goes low until the next valid clock
event. If the selected clock is restored, the input bad detector
waits 4 full clock periods before clearing the flag and returning to
normal operation. If CLK_SEL is changed to select a valid input
clock, the output will stay low for one full peiod of the new input
clock, then return to normal operation.
event. If DIV_SEL is changed, the output will transition from the
low state following the selected divide when a valid input clock is
restored.
is restored while the OEx is low, the output will transition from
the HighZ to a low state to ensure a clean rising edge of the
first output clock when the Oex is pulled high again.
AD
B
B
I
AD
NPUT
AD
I
NPUT
I
NPUT
T
IMING
T
T
IMING
IMING
D
IAGRAM
D
D
ICS870S208BK REV. A NOVEMBER 9, 2007
IAGRAM
IAGRAM
PRELIMINARY