ICS853054AGT IDT, Integrated Device Technology Inc, ICS853054AGT Datasheet - Page 8

• Manufacturer Part Number: ICS853054AGT
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Multiplexerr

Specifications of ICS853054AGT

• Number Of Clock Inputs: 4
• Mode Of Operation: Differential
• Output Frequency: 3200MHz
• Output Logic Level: ECL/LVPECL
• Operating Supply Voltage (min): -2.375/2.375V
• Operating Supply Voltage (typ): -2.5/-3.3/3.3V
• Operating Supply Voltage (max): -3.465/3.465V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: CML/LVDS/LVPECL/SSTL
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Not Compliant

IDT™ / ICS™ 4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
LVPECL C
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
and V
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
F
F
853054AG
F
IGURE
IGURE
IGURE
3.3V
CMR
2C. H
2A. H
3.3V LVPECL
2E. H
3.3V
3.3V
input requirements. Figures 2A to 2E show inter-
LVPECL
R5
100 - 200
CML
BY A
BY A
BY A
LOCK
I
I
I
P
P
P
Integrated
Circuit
Systems, Inc.
ER
ER
ER
3.3V LVPECL D
R6
100 - 200
3.3V LVPECL D
CML D
Zo = 50 Ohm
Zo = 50 Ohm
C
C
C
Zo = 50 Ohm
Zo = 50 Ohm
I
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
LOCK
LOCK
NPUT
S PCLK/nPCLK I
S PCLK/nPCLK I
S PCLK/nPCLK I
RIVER
SWING
I
NTERFACE
C1
C2
3.3V
R1
50
and V
3.3V
R3
125
R1
84
3.3V
R3
84
R1
125
R2
50
RIVER
RIVER WITH
R4
125
OH
R2
84
R4
84
PCLK
nPCLK
R2
125
must meet the V
3.3V
www.icst.com/products/hiperclocks.html
PCLK
nPCLK
NPUT
NPUT
NPUT
HiPerClockS
PCLK/nPCLK
3.3V
PCLK
nPCLK
AC C
Input
3.3V
D
D
D
HiPerClockS
RIVEN
RIVEN
RIVEN
HiPerClockS
PCLK/nPCLK
OUPLE
PP
8
8
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
F
F
IGURE
IGURE
3.3V
2D. H
2B. H
4:1, D
LVDS
2.5V
LVPECL/ECL C
SSTL
BY A
BY AN
Zo = 50 Ohm
Zo = 50 Ohm
I
I
P
P
ER
ER
IFFERENTIAL
3.3V LVDS D
C
C
Zo = 60 Ohm
Zo = 60 Ohm
SSTL
LOCK
LOCK
R5
100
S PCLK/nPCLK I
S PCLK/nPCLK I
IN
D
2.5V
R3
120
RIVER
R1
120
C1
C2
RIVER
-
LOCK
TO
R4
120
R2
120
3.3V
R3
1K
R1
1K
-3.3V
PCLK
nPCLK
R4
1K
M
R2
1K
3.3V
REV. A JANUARY 5, 2006
NPUT
NPUT
ULTIPLEXER
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
3.3V
OR
D
D
HiPerClockS
PCL K/n PC LK
RIVEN
RIVEN
2.5V
ICS853054
TSD