ICS85357AG-11T IDT, Integrated Device Technology Inc, ICS85357AG-11T Datasheet

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ICS85357AG-11T

Manufacturer Part Number
ICS85357AG-11T
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Multiplexerr
Datasheet

Specifications of ICS85357AG-11T

Number Of Clock Inputs
4
Mode Of Operation
Single-Ended
Output Logic Level
ECL/LVPECL
Operating Supply Voltage (min)
-3.135/3.135V
Operating Supply Voltage (typ)
-3.3/3.3V
Operating Supply Voltage (max)
-3.465/3.465V
Package Type
TSSOP
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Not Compliant
B
XT ALOUT1
XT ALOUT2
XT ALOUT3
G
The
Oscillator-to-3.3V LVPECL / ECL Multiplexer . The ICS85357-
11 has 4 selectable crystal inputs. The device can support
10MHz to 27MHz parallel resonant crystals by connecting
external capacitors between XTALIN/XTALOUT and ground.
The select pins have internal pulldown resistors and leaving
one input unconnected (pulled to logic low by the internal
resistor) will transform the device into a 2:1 multiplexer. The
SEL1 lead is the most significant line and the binary number
applied to the select pins will select the same numbered data
input (i.e., 00 selects XTALIN0/XTALOUT0).
XT ALOUT0
85357AG-11
XTALIN1
XTALIN2
XTALIN3
XTALIN0
LOCK
ENERAL
ICS85357-11
D
OSC
OSC
OSC
OSC
IAGRAM
D
ESCRIPTION
is
a
00
11
01
10
SEL1
4:1
SEL0
or
2:1,
Crystal
www.idt.com
1
Q0
nQ0
F
P
4:1
One differential 3.3V LVPECL output
4:1 or 2:1 Crystal Oscillator Multiplexer
Supports parallel resonant crystals with a frequency range
of 10MHz to 27MHz. The oscillator circuit is optimized for
parallel resonant mode, and will require external capacitance
Maximum output frequency: 27MHz
LVCMOS/LVTTL SEL0 and SEL1 inputs have
internal pulldown resistors
LVPECL mode operating voltage supply range:
V
ECL mode operating voltage supply range:
V
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in both standard (R0HS 5) and lead-free
(RoHS 6) packages
EATURES
IN
CC
CC
= 3.135V to 3.465V, V
= 0V, V
OR
A
4.40mm x 6.50mm x 0.92mm body package
SSIGNMENT
2:1, C
EE
= -3.135V to -3.465V
XTALOUT0
XTALOUT1
XTALOUT2
XTALOUT3
XTALIN0
XTALIN1
XTALIN2
XTALIN3
LVPECL / ECL M
V
RYSTAL
V
ICS85357-11
20-Lead TSSOP
CC
EE
G Package
Top View
1
2
3
4
5
6
7
8
9
10
EE
= 0V
O
20
19
18
17
16
15
14
13
12
11
ICS85357-11
SCILLATOR
V
SEL1
SEL0
V
Q0
nQ0
V
nc
nc
V
CC
CC
CC
EE
REV. D OCTOBER 4, 2010
ULTIPLEXER
-
TO
-3.3V

Related parts for ICS85357AG-11T

ICS85357AG-11T Summary of contents

Page 1

G D ENERAL ESCRIPTION The ICS85357- 4:1 Oscillator-to-3.3V LVPECL / ECL Multiplexer . The ICS85357- 11 has 4 selectable crystal inputs. The device can support 10MHz to 27MHz parallel resonant crystals by connecting external capacitors between XTALIN/XTALOUT and ...

Page 2

ABLE IN ESCRIPTIONS ...

Page 3

BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs, V -0. Package Thermal Impedance, JA Storage Temperature, T -65°C to 150°C STG T 4A ABLE ...

Page 4

P ARAMETER LVPECL V EE -1.3V ± 0.165V 3. UTPUT OAD EST IRCUIT nQ0 Q0 Pulse Width t PERIOD t PW odc = t PERIOD UTPUT ...

Page 5

RYSTAL NPUT NTERFACE A crystal can be characterized for either series or parallel mode operation. The ICS85357-11 has a built-in crystal oscillator circuit. This interface can accept either a series or parallel crystal without additional components and ...

Page 6

T LVPECL O ERMINATION FOR UTPUTS The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that gen- ...

Page 7

This section provides information on power dissipation and junction temperature for the ICS85357-11. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85357-11 is the sum of the core power plus the power ...

Page 8

Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 3. F IGURE T o calculate worst case power dissipation into the ...

Page 9

ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains ...

Page 10

ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MO-153 85357AG-11 4:1 2: TSSOP EAD 10 ACKAGE IMENSIONS ...

Page 11

T 11 ABLE RDERING NFORMATION ...

Page 12

...

Page 13

We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...

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