ICS8344AY-01T IDT, Integrated Device Technology Inc, ICS8344AY-01T Datasheet

ICS8344AY-01T

Manufacturer Part Number
ICS8344AY-01T
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of ICS8344AY-01T

Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
250MHz
Output Logic Level
LVCMOS/LVTTL
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465V
Package Type
LQFP
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
48
Quiescent Current
95mA
Lead Free Status / RoHS Status
Not Compliant
LOW SKEW, 1-TO-24 DIFFERENTIAL-
TO-LVCMOS/LVTTL FANOUT BUFFER
B
IDT
G
standard differential input levels. The ICS8344-01 is designed
to translate any differential signal level to LVCMOS/LVTTL lev-
els. The low impedance LVCMOS/LVTTL outputs are designed
to drive 50Ω series or parallel terminated transmission lines.
The effective fanout can be increased to 48 by utilizing the
ability of the outputs to drive two series terminated lines.
Redundant clock applications can make use of the dual clock
inputs which also facilitate board level testing. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin. The outputs are driven low when disabled.
The ICS8344-01 is characterized at full 3.3V, full 2.5V and mixed
3.3V input and 2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics make
the ICS8344-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
HiPerClockS™
IC S
CLK_SEL
LOCK
CLK_EN
ENERAL
nCLK0
nCLK1
/ ICS
CLK0
CLK1
OE
Pulldown
Pulldown
Pullup
Pulldown
Pullup
LVCMOS/LVTTL FANOUT BUFFER
Pullup
Pullup
D
The ICS8344-01 is a low voltage, low skew
fanout buffer and a member of the HiPerClockS ™
family of High Performance Clock Solutions from
IDT. The ICS8344-01 has two selectable clock in-
puts. The CLKx, nCLKx pairs can accept most
IAGRAM
D
ESCRIPTION
0
1
LE
nD
Q
Q0:Q7
Q8:Q15
Q16:Q23
1
F
• Twenty-four LVCMOS/LVTTL outputs,
• Two selectable differential CLKx, nCLKx inputs
• CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the
• Output frequency up to 250MHz
• Translates any single ended input signal to LVCMOS/LVTTL
• Synchronous clock enable
• Additive phase jitter RMS: 0.21ps (typical)
• Output skew: 200ps (maximum)
• Part-to-part skew: 900ps (maximum)
• Bank skew: 85ps (maximum)
• Propagation delay: 5ns (maximum)
• Output supply modes:
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
7Ω typical output impedance
following input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
with resistor bias on nCLK input
Core/Output
3.3V/3.3V
2.5V/2.5V
3.3V/2.5V
packages
EATURES
P
GND
GND
V
V
Q16
Q17
Q18
Q19
Q20
Q21
Q22
Q23
IN
DDO
DDO
A
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
SSIGNMENT
7mm x 7mm x 1.4mm
ICS8344-01
ICS8344AY-01 REV. C SEPTEMBER 9, 2008
48-Lead LQFP
package body
Y Package
Top View
ICS8344-01
36
35
34
33
32
31
30
29
28
27
26
25
Q7
Q6
V
GND
Q5
Q4
Q3
Q2
V
GND
Q1
Q0
DDO
DDO

Related parts for ICS8344AY-01T

ICS8344AY-01T Summary of contents

Page 1

... A IN SSIGNMENT Q16 1 Q17 DDO Q0:Q7 GND 4 Q18 5 Q19 6 Q8:Q15 Q20 7 Q21 DDO Q16:Q23 GND 10 Q22 11 Q23 ICS8344- DDO ICS8344-01 33 GND 32 Q5 48-Lead LQFP 31 Q4 7mm x 7mm x 1.4mm 30 Q3 package body Package 28 V DDO Top View 27 GND ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ...

Page 2

... ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER ABLE IN ESCRIPTIONS ABLE IN HARACTERISTICS IDT ™ / ICS ™ LVCMOS/LVTTL FANOUT BUFFER Ω Ω Ω ICS8344AY-01 REV. C SEPTEMBER 9, 2008 kΩ kΩ Ω ...

Page 3

... ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER T 3A ABLE UTPUT NABLE UNCTION 3B ABLE LOCK ELECT UNCTION 3C ABLE LOCK NPUT UNCTION ABLE IDT ™ / ICS ™ LVCMOS/LVTTL FANOUT BUFFER ABLE ABLE ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ...

Page 4

... Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability 3.3V±5 0° DDO 3.3V±5 2.5V±5 DDO 2.5V±5 0° DDO 3.3V±5 DDO 70° 0°C 70° 70° 0°C 70° ICS8344AY-01 REV. C SEPTEMBER 9, 2008 µ A µ A µ A µ ...

Page 5

... LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER T 4E. LVCMOS/LVTTL DC C ABLE HARACTERISTICS 4F. LVCMOS/LVTTL DC C ABLE HARACTERISTICS IDT ™ / ICS ™ LVCMOS/LVTTL FANOUT BUFFER , V = 3.3V±5 2.5V±5 DDO 2.5V±5 DDO 0°C 70° 0°C 70° ICS8344AY-01 REV. C SEPTEMBER 9, 2008 µ A µ A µ A µ µ A µ A µ A µ ...

Page 6

... IDT ™ / ICS ™ LVCMOS/LVTTL FANOUT BUFFER , 3.3V±5 0° DDO 3.3V±5 2.5V±5 DDO 2.5V±5 0° DDO 70° 0°C 70° 70° ICS8344AY-01 REV. C SEPTEMBER 9, 2008 µ A µ A µ A µ µ A µ A µ A µ µ A µ A µ A µ ...

Page 7

... ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER ABLE HARACTERISTICS 2.5V ± 5 0°C 70° DDO IDT ™ / ICS ™ LVCMOS/LVTTL FANOUT BUFFER = 3.3V±5 3.3V ± 5%, V DDO DD DDO ≤ ≤ 2.5V ± 5 ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ...

Page 8

... FFSET ROM ARRIER REQUENCY device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. 8 Additive Phase Jitter @ ) Z ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ...

Page 9

... SCOPE GND LVCMOS -1.25V±5% 3.3V C /2.5V O ORE V DD SCOPE nCLK0, nCLK1 V Qx CLK0, CLK1 GND D IFFERENTIAL UTPUT KEW 9 SCOPE DDO UTPUT OAD EST IRCUIT Cross Points NPUT EVEL V DDO 2 V DDO 2 tsk(o) ICS8344AY-01 REV. C SEPTEMBER 9, 2008 V CMR ...

Page 10

... LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER nCLK0, nCLK1 CLK0, CLK1 Q0:Q23 ROPAGATION ELAY 80% 20% Clock t Outputs UTPUT ISE ALL IME IDT ™ / ICS ™ LVCMOS/LVTTL FANOUT BUFFER Q0:Q23 O D UTPUT UTY 80% 20 DDO PERIOD 100% odc = t PERIOD YCLE ULSE IDTH ERIOD ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ...

Page 11

... R2/R1 = 0.609. VDD R1 1K V_REF nCLKx C1 0. INGLE NDED IGNAL RIVING NPUT AND UTPUT INS O UTPUTS LVCMOS O All unused LVCMOS output can be left floating. There should be no trace attached 3.3V, V_REF should be 1.25V DD CLKx D I IFFERENTIAL NPUT : : UTPUT ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ...

Page 12

... HiPerClockS Input NPUT RIVEN OUPLE 12 3. Ohm CLK Ohm nCLK HiPerClockS LVPECL Input 2B CLK/nCLK LOCK NPUT 3.3V LVPECL D RIVER Ohm LVDS_Driv er R1 100 Ohm 2D CLK/nCLK LOCK NPUT 3.3V LVDS D RIVER ICS8344AY-01 REV. C SEPTEMBER 9, 2008 D RIVEN BY 3.3V CLK nCLK Receiv er D RIVEN BY ...

Page 13

... IDT ™ / ICS ™ LVCMOS/LVTTL FANOUT BUFFER R I ELIABILITY NFORMATION 48 L LQFP EAD θ θ θ θ θ by Velocity (Linear Feet per Minute 67.8°C/W 47.9°C/W 13 200 500 55.9°C/W 50.1°C/W 42.1°C/W 39.4°C/W ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ...

Page 14

... ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER ACKAGE UTLINE UFFIX FOR T ABLE S Y Reference Document: JEDEC Publication 95, MS-026 IDT ™ / ICS ™ LVCMOS/LVTTL FANOUT BUFFER LQFP EAD ACKAGE IMENSIONS θ θ θ θ θ ° ° ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ...

Page 15

... LVCMOS/LVTTL FANOUT BUFFER Package Shipping Packaging 48 Lead LQFP 48 Lead LQFP 1000 tape & reel 48 lead "Lead-Free" LQFP 48 lead "Lead-Free" LQFP 1000 tape & reel 15 Temperature tray 0°C to 70°C 0°C to 70°C tray 0°C to 70°C 0°C to 70°C ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ...

Page 16

... ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER IDT ™ / ICS ™ LVCMOS/LVTTL FANOUT BUFFER ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ...

Page 17

ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject ...

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