ICS8534AY-01T IDT, Integrated Device Technology Inc, ICS8534AY-01T Datasheet - Page 2

• Manufacturer Part Number: ICS8534AY-01T
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS8534AY-01T

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 500MHz
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TQFP EP
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
33, 48, 49, 64
1, 16, 17, 32,
2, 3, 12, 13
ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Number
14, 15
18, 19
20, 21
22, 23
24, 25
26, 27
28, 29
30, 31
34, 35
36, 37
38, 39
40, 41
42, 43
44, 45
46, 47
50, 51
52, 53
54, 55
56, 57
58, 59
60, 61
10
11
59
4
5
6
7
8
9
nQ21, Q21
nQ20, Q20
nQ19, Q19
nQ18, Q18
nQ17, Q17
nQ16, Q16
nQ15, Q15
nQ14, Q14
nQ13, Q13
nQ12, Q12
nQ11, Q11
nQ10, Q10
CLK_SEL
nQ9, Q9
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
nPCLK
Name
PCLK
V
nCLK
CLK
V
V
OE
CCO
nc
CC
EE
Unused
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Power
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pulldown
Pullup/
Pullup/
Pullup
Pullup
Description
Output supply pins for LVPECL outputs.
No connect.
Core supply pin for LVPECL outputs.
Non-inverting differential clock input.
Inverting differential clock input. Pulled to
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. Pulled to
Negative supply pin.
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are disabled and drive differential low:
Qx = LOW, nQx = HIGH. LVCMOS / LVTTL interface levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
2
ICS8534AY-01 REV. A OCTOBER 27, 2008
2
/
3
V
CC
.
2
/
3
V
CC
.