8535-01PG8 IDT, Integrated Device Technology Inc, 8535-01PG8 Datasheet
8535-01PG8
Specifications of 8535-01PG8
Related parts for 8535-01PG8
8535-01PG8 Summary of contents
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... LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO- 3.3V LVPECL FANOUT BUFFER G D ENERAL ESCRIPTION The ICS8535- low skew, high performance IC S 1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL fanout HiPerClockS™ buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS8535-01 has two single ended clock inputs. the single ended clock input accepts LVCMOS or LVTTL input lev- els and translate them to 3 ...
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... ICS8535-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER ABLE IN ESCRIPTIONS ABLE IN HARACTERISTICS IDT ™ / ICS ™ 3.3V LVPECL FANOUT BUFFER ICS8535AG-01 REV. F OCTOBER 27, 2008 ...
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... LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER T 3A ABLE ONTROL NPUT UNCTION Disabled CLK0, CLK1 CLK_EN nQ0:nQ3 Q0: ABLE LOCK NPUT UNCTION ABLE IDT ™ / ICS ™ 3.3V LVPECL FANOUT BUFFER ABLE CLK_EN T D IGURE IMING IAGRAM Enabled ICS8535AG-01 REV. F OCTOBER 27, 2008 ...
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... DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability 3.3V±5 0° 3.3V±5 0°C HARACTERISTICS 3.3V±5 0°C 70° 70° 70° ICS8535AG-01 REV. F OCTOBER 27, 2008 µ A µ A µ A µ ...
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... ICS8535-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER 3.3V±5%, T ABLE HARACTERISTICS IDT ™ / ICS ™ 3.3V LVPECL FANOUT BUFFER = 0°C 70° ƒ ICS8535AG-01 REV. F OCTOBER 27, 2008 ...
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... Input/Output Additive Phase Jitter 100k FFSET ROM ARRIER REQUENCY Z meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment 156.25MHz = 0.09ps (typical) 10M 100M ) ICS8535AG-01 REV. F OCTOBER 27, 2008 ...
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... LVPECL FANOUT BUFFER M I EASUREMENT NFORMATION SCOPE PART 1 nQx Qx Qx PART 2 nQy nQx ART TO ART Clock 20% Outputs UTPUT ISE nQ0:nQ3 Q0: UTPUT UTY 7 tsk(pp) S KEW 80% 80 ALL IME PERIOD t PW odc = x 100% t PERIOD YCLE ULSE IDTH ERIOD ICS8535AG-01 REV. F OCTOBER 27, 2008 20% ...
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... Other suitable clock layouts may exist and it would be recommended that the board design- ers simulate to guarantee compatibility across all printed circuit and clock component process variations. FIN FOUT RTT T ERMINATION 8 : UTPUT 3.3V 125 125 FIN 2B. LVPECL O T IGURE UTPUT ERMINATION ICS8535AG-01 REV. F OCTOBER 27, 2008 ...
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... ICS8535-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER S E CHEMATIC XAMPLE Figure 3 shows a schematic example of the ICS8535-01. In this example, the CLK0 input is selected. The decoupling capacitors 3. Ohm Ohm R13 43 LVCMOS F IGURE IDT ™ / ICS ™ 3.3V LVPECL FANOUT BUFFER should be physically located near the power pin. For ICS8535-01, the unused clock outputs can be left floating ...
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... Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8535-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. ...
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... Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT ™ / ICS ™ 3.3V LVPECL FANOUT BUFFER LVPECL D C IGURE RIVER IRCUIT AND – 0.9V CC_MAX – OH_MAX CC_MAX OH_MAX [( OL_MAX CC_MAX OL_MAX OUT ERMINATION load, and a termination ] * ( CC_MAX OH_MAX - CC_MAX OL_MAX ICS8535AG-01 REV. F OCTOBER 27, 2008 ...
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... T 7B ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T C RANSISTOR OUNT The transistor count for ICS8535-01 is: 412 IDT ™ / ICS ™ 3.3V LVPECL FANOUT BUFFER R I ELIABILITY NFORMATION 20 L TSSOP EAD by Velocity (Linear Feet per Minute 114.5°C/W 73.2° ...
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... ICS8535-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER ACKAGE UTLINE UFFIX FOR IDT ™ / ICS ™ 3.3V LVPECL FANOUT BUFFER TSSOP EAD T 8A TSSOP ABLE ACKAGE IMENSIONS FOR ° JEDEC P 95, MO-153 EFERENCE OCUMENT UBLICATION ° ICS8535AG-01 REV. F OCTOBER 27, 2008 ...
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... ICS8535-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER ACKAGE UTLINE UFFIX FOR IDT ™ / ICS ™ 3.3V LVPECL FANOUT BUFFER VFQFN EAD T 8B ABLE ACKAGE IMENSIONS FOR Reference Document: JEDEC Publication 95, MO-220 VFQFN EAD ICS8535AG-01 REV. F OCTOBER 27, 2008 ...
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... ICS ™ 3.3V LVPECL FANOUT BUFFER " " " " " " " " " " ° & ° ° & ° ° & ° ° & ° ICS8535AG-01 REV. F OCTOBER 27, 2008 ° ° ° ° ° ° ° ° ...
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... LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER " " IDT ™ / ICS ™ 3.3V LVPECL FANOUT BUFFER ± " " ± " " " " " " " " " " " " " " " " ICS8535AG-01 REV. F OCTOBER 27, 2008 ...
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... ICS8535-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) © ...