IDT82V3012PV IDT, Integrated Device Technology Inc, IDT82V3012PV Datasheet - Page 13

• Manufacturer Part Number: IDT82V3012PV
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLLr

Specifications of IDT82V3012PV

• Number Of Elements: 1
• Supply Current: 60mA
• Pll Input Freq (min): 8KHz
• Pll Input Freq (max): 19.44MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Output Frequency Range: Up to 155.52MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Pin Count: 56
• Lead Free Status / RoHS Status: Not Compliant

2.7
a Limiter, a Loop Filter, a Digital Control Oscillator and Divider.
2.7.1
reference signal from the TIE Control Circuit with the feedback signal
from the Frequency Select Circuit, and outputs an error signal
corresponding to the phase difference. This error signal is sent to the
Limiter circuit for phase slope control.
Functional Description
IDT82V3012
As shown in
In the Normal mode, the Phase Detector compares the virtual
DPLL BLOCK
PHASE DETECTOR (PHD)
Figure -
7, the DPLL Block consists of a Phase Detector,
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Ref1
Ref2
Ref1
Ref2
Figure - 6 Reference Switch with TIE Control Block Disabled
Figure - 5 Reference Switch with TIE Control Block Enabled
13
Phase Detector and the Limiter are inactive, and the input reference
signal is not used.
2.7.2
maximum output phase slope is limited to 5 ns per 125 µs for all input
transient conditions. This well meets the AT&T TR62411 and Telcordia
GR-1244-CORE specifications, which specify the maximum phase slope
of 7.6 ns per 125 µs and 81 ns per 1.326 ms respectively.
In the Freerun or Holdover mode, the Frequency Select Circuit, the
The Limiter is used to limit the phase slope. It ensures that the
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
LIMITER
Output Clock
Output Clock
Input Clock
Input Clock
February 6, 2009