IDT82V3012PV IDT, Integrated Device Technology Inc, IDT82V3012PV Datasheet - Page 14

• Manufacturer Part Number: IDT82V3012PV
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLLr

Specifications of IDT82V3012PV

• Number Of Elements: 1
• Supply Current: 60mA
• Pll Input Freq (min): 8KHz
• Pll Input Freq (max): 19.44MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Output Frequency Range: Up to 155.52MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Pin Count: 56
• Lead Free Status / RoHS Status: Not Compliant

Phase Detector, limits the phase slope within 5 ns per 125 µs and sends
the limited signal to the Loop Filter.
the input reference within 500 ms, which is much shorter than that in the
Normal mode.
2.7.3
011 and AT&T TR62411 requirements. It works similarly to a first order
low pass filter with 2.1 Hz cutoff frequency for the four valid input
frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz).
directly or through the Fraction blocks, in which E1, T1, C6 and C19
signals are generated.
2.7.4
Fraction_C19, Fraction_C6 and Fraction_T1 blocks generate C19, C6
and T1 signals respectively.
Functional Description
IDT82V3012
In the Normal mode, the Limiter receives the error signal from the
In the Fast Lock mode, the Limiter is disabled, and the DPLL locks to
The Loop Filter ensures that the jitter transfer meets the ETS 300
The output of the Loop Filter goes to the Digital Control Oscillator
By applying some algorithms to the incoming E1 signal, the
LOOP FILTER
FRACTION BLOCK
Loop Filter
Fraction_C19
Fraction_T1
Fraction_C6
Limiter
FLOCK
Detector
Phase
19.44 MHz
Figure - 7 DPLL Block Diagram
Virtual Reference
Feedback Signal
24.704 MHz
32.768 MHz
25.248 MHz
APLL
14
155.52 MHz
2.7.5
signals from Loop Filter or Fraction blocks. Based on the values of the
received signals, the DCO generates four digital outputs: 19.44 MHz,
25.248 MHz, 32.768 MHz and 24.704 MHz for C19, C6, E1 and T1
dividers respectively.
that generated by storage techniques.
that of the master clock.
2.7.6
and the input phase offset is small enough so that no slope limiting is
exhibited, the LOCK pin will be set high.
2.7.7
generate totally 9 types of clock signals and 7 types of framing signals
All these output signals are synchronous to F8o.
In the Normal mode, the DCO receives four limited and filtered
In the Holdover mode, the DCO is running at the same frequency as
In the Freerun mode, the DCO is running at the same frequency as
If the output frequency of the DPLL is identical to the input frequency,
The Output Interface uses three output signals from the DCO to
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
IN_sel
Output Interface
OUTPUT INTERFACE
C19_Divider
DIGITAL CONTROL OSCILLATOR (DCO)
LOCK INDICATOR
F1_sel1 F1_sel0
T1_Divider
E1_Divider
C6_Divider
Frequency
Selection
Circuit 1
Fx_sel1 Fx_sel0 (x = 0 or 1)
F0_sel1 F0_sel0
Frequency
Selection
Circuit 0
C1.5o
C3o
C2o
C4o
C8o
C16o
C32o
F0o
F8o
F16o
F32o
RSP
TSP
C2/C1.5
C6o
C19POS
C19NEG
C19o
F19o
February 6, 2009