UPD4991ACX Renesas Electronics America, UPD4991ACX Datasheet - Page 25

• Manufacturer Part Number: UPD4991ACX
• Manufacturer: Renesas Electronics America

Specifications of UPD4991ACX

• Lead Free Status / RoHS Status: Supplier Unconfirmed

(3) CONTROL REGISTER 2 (address 0E
This register controls the alarm signal output to TP1 and the interval signal output to TP2. Figure 2-7 shows
the diagram of the TP pin control block, and Table 2-6 lists the commands of CONTROL REGISTER 2.
Alarm signal control block
(c) CLOCK STOP and CLOCK WAIT (stops time counter)
Both these commands disable input of the clock (1 Hz) to the watch counter and stop the watch.
CLOCK STOP is used when time data is written (be sure to stop the watch when writing time data).
CLOCK WAIT is used when time data is read. This is to prevent a new count from occurring and the CPU
from reading wrong data when time data is read. Time data can be also read by using the BUSY signal
or by reading the time data two times, without using CLOCK WAIT.
If the clock input is resumed within 0.5 seconds after the watch has been stopped by CLOCK STOP or
CLOCK WAIT, the real time is not delayed (if a carry occurs from 1-second digit while the watch is stopped,
adjustment of +1 second is made after the clock input is resumed).
Auto reset
or not?
Comparator Coincidence signal
Alarm
register
Time
counter
TP1 function control
"H"
2048 Hz
1 Pulse
BUSY
Comparison:
Valid/invalid
1 Hz
Figure 2-7. TP Pin Control Block Diagram
"L"
CHAPTER 2 OPERATIONS
Control
register 2
H
Switch
Multi-
plexer
) [during write]
Forced output
Select
Output control
TP1 pin
23