IDT77V1264L200PGI IDT, Integrated Device Technology Inc, IDT77V1264L200PGI Datasheet - Page 37

• Manufacturer Part Number: IDT77V1264L200PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1264L200PGI

• Number Of Channels: 4
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

LED Driver and HEC Status/Control Registers
Addresses: 0x02, 0x12, 0x22, 0x32
6
5
4
3
2
1,0
Addresses: 0x03, 0x13, 0x23, 0x33
7
6
5
4, 3
2
1
0
1.
IDT77V1264L200
Bit
Bit
When Bits [1:0] in the Diagnostic Control Registers are set to 10, the PHY loopback mode works only if clock multiplier is 1x. For higher multiplies, these bits must be set to 01.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
Type
Type
0 = UTOPIA
1 = tri-state
0 = normal
0 = normal
0 = normal
00 = normal
0
0 = enable checking
0 = enable calculate &
replace
00 = 1 cycle
1 = empty
1
1
Initial State
Initial State
RXCLAV Operation Select - (for Utopia 1 mode) The UTOPIA standard dictates that during cell mode operation, if the
receive FIFO no longer has a complete cell available for transfer from PHY, RXCLAV is deasserted following transfer of
the last byte out of the PHY to the upstream system. With this bit set, early deassertion of this signal will occur coinci-
dent with the end of Payload byte 44 (as in octet mode for TXCLAV). This provides early indication to the upstream
system of this impending condition.
Single/Multi-PHY configuration select - (applicable and writable only in Utopia 1 mode)
0 = single:
1 = Multi-PHY mode: Tri-state RXDATA, RXPARITY and RXSOC when RXEN = 1
RFLUSH = Clear Receive FIFO - This signal is used to tell the TC to flush (clear) all data in the receive FIFO. The TC
signals this completion by clearing this bit.
Insert Transmit Payload Error - Tells TC to insert cell payload errors in transmitted cells. This can be used to test
error detection and recovery systems at destination station, or, under loopback control, at the local receiving station.
This payload error is accomplished by flipping bit 0 of the last cell payload byte.
Insert Transmit HEC Error - Tells TC to insert HEC error in Byte 5 of cell. This can be used to test error detection and
recovery systems in downstream switches, or, under loopback control, the local receiving station. The HEC error is
accomplished by flipping bit 0 of the HEC byte.
Loopback Control
bit # 1
Reserved
Disable Receive HEC Checking (HEC Enable) - When not set, the HEC is calculated on first 4 bytes of received cell,
and compared against the 5th byte. When set (= 1), the HEC byte is not checked.
Disable Transmit HEC Calculate & Replace - When set, the 5th header byte of cells queued for transmit is not
replaced with the HEC calculated across the first four bytes of that cell.
RXREF Pulse Width Select - See notes about 8KHz Timing Marker in the Functional Description Section.
bit #
FIFO Status
TXLED Status
RXLED Status
0 = "Standard UTOPIA RXCLAV’
1 = "Cell mode = Byte mode"
0
1
1
0
4
0
0
1
1
0
0 Normal mode (receive from network)
0 PHY Loopback (with clock recovery)
1 Line Loopback
1 PHY Loopback (with clock recovery)
3 .
0 RXREF active for 1 OSC cycle
1 RXREF active for 2 OSC cycles
0 RXREF active for 4 OSC cycles
1 RXREF active for 8 OSC cycles
1 = TxFIFO empty
Never tri-state RXDATA, RXPARITY and RXSOC
0 = Cell Transmitted
0 = Cell Received
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0 = TxFIFO not empty
1 = Cell Not Received
1 = Cell Not Transmitted
Function
Function
1
1
December 2004