IDT77V1264L200PGI IDT, Integrated Device Technology Inc, IDT77V1264L200PGI Datasheet - Page 5

• Manufacturer Part Number: IDT77V1264L200PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1264L200PGI

• Number Of Channels: 4
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

SE
TXLED[3:0]
TXREF
Signal Name
AGND
AVDD
GND
VDD
Signal Name
RXADDR[4:0] 53, 52, 51, 49, 48
RXCLAV
RXCLK
RXDATA[15:0] 59, 60, 61, 62, 63, 64, 65,
RXEN
RXPARITY
RXSOC
TXADDR[4:0]
TXCLAV
TXCLK
TXDATA[15:0] 32, 31, 30, 29, 28, 27, 26,
TXEN
TXPARITY
TXSOC
IDT77V1264L200
102
12, 13, 14, 15
10
Pin Number
112, 117, 118, 123, 124,
127, 129, 130, 135, 136, 141
113, 116, 119, 122, 125,
128, 131, 134, 137, 140
2, 11, 44, 50, 56, 67, 77, 83,
86, 97, 107, 111, 142
1, 5, 16, 38, 45, 57, 68, 78,
84, 92, 104, 108
Pin Number
54
46
66, 69, 70, 71, 72, 73, 74,
75, 76
47
58
55
36, 37, 39, 40, 41
42
43
25, 24, 23, 22, 21, 20, 19,
18, 17
34
33
35
In
Out
In
I/O
____
____
____
____
I/O
In
Out
In
Out
In
Out
Out
In
Out
In
In
In
In
In
16-BIT UTOPIA 2 Signals (MODE[1:0] = 00)
Reserved signal. This input must be connected to logic low.
Ports 3 through 0 Transmit LED driver. Goes low for 223 cycles of OSC, beginning with TXSOC when this
port receives a cell for transmission. 8 mA drive current both high and low. One per port.
Transmit Reference. Synchronous to OSC. On the falling edge, an X_8 command byte is inserted into the
transmit data stream. Logic for this signal is programmed in register 0x40. Typical application is WAN timing.
Signal Description
Analog ground. AGND supply a ground reference to the analog portion of the ship, which sources a more
constant current than the digital portion.
Analog power supply 3.3 ± 0.3V AVDD supply power to the analog portion of the chip, which draws a more
constant current than the digital portion.
Digital Ground.
Digital power supply. 3.3 ± 0.3V.
Signal Description
Utopia 2 Receive Address Bus. This bus is used in polling and selecting the receive port. The port addresses
are defined in bits [4:0] of the Enhanced Control Registers.
Utopia 2 Receive Cell Available. Indicates the cell available status of the addressed port. It is asserted when
a full cell is available for retrieval from the receive FIFO. When non of the four ports is addressed. RXCLAV is
high impedance.
Utopia 2 Receive Clock. This is a free running clock input.
Utopia 2 Receive Data. When one of the four ports is selected, the 77V1264L200 transfers received cells to
an ATM device across this bus. Also see RXPARITY.
Utopia 2 Receive Enable. Driven by an ATM device to indicate its ability to receive data across the RXDATA
bus.
Utopia 2 Receive Data Parity. Odd parity over RXDATA[15:0].
Utopia 2 Receive Start of Cell. Asserted coincident with the first word of data for each cell on RXDATA.
Utopia 2 Transmit Address Bus. This bus is used in polling and selecting the transmit port. The port
addresses are defined in bits [4:0] of the Enhanced Control Registers.
Utopia 2 Transmit Cell Available. Indicates the availability of room in the transmit FIFO of the addressed port
for a full cell. When none of the four ports is addressed, TXCLAV is high impedance.
Utopia Transmit Clock. This is a free running clock input.
Utopia 2 Transmit Data. An ATM device transfers cells across this bus to the 77V1264L200 for transmission.
Also see TXPARITY.
Utopia 2 Transmit Enable. Driven by an ATM device to indicate it is transmitting data across the TXDATA
bus.
Utopia 2 Transmit Data Parity. Odd parity across TXDATA[15:0]. Parity is checked and errors are indicated in
the Interrupt Status Registers, as enabled in the Master Control Registers. No other action is taken in the
event of an error. Tie high or low if unused.
Utopia 2 Transmit Start of Cell. Asserted coincident with the first word of data for each cell on TXDATA.
Table 2 Signal Descriptions (Part 2 of 3)
Power Supply Signals
5 of 49
December 2004