IDT77V106L25TFI8 IDT, Integrated Device Technology Inc, IDT77V106L25TFI8 Datasheet - Page 9

• Manufacturer Part Number: IDT77V106L25TFI8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V106L25TFI8

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

available) to indicate that it has room in its transmit FIFO to accept at least one
53-byte ATM cell. When the ATM layer device is ready to begin passing the
cell, it asserts TXEN (transmit enable) and TXSOC (start of cell), coincident with
the first byte of the cell on TXDATA. TXEN can remain asserted for the duration
of the cell transfer, or the ATM device may deassert TXEN at any time once
the cell transfer has begun; data is transferred only when TXEN is asserted.
to receive data. As with transmit, it may be asserted or deasserted at any time.
mode as determined by bit 1 in the Master Control Register. In cell-mode, which
is the default, the 77V106L25 does not assert TXCLAV until it has enough room
in it’s transmit FIFO to accept a complete cell, and doesn’t assert RXCLAV until
it has a complete cell in the receive FIFO. It will not deassert TXCLAV or
RXCLAV until at or near the end of the transfer of a cell.
TXCLK
TXCLAV
TXEN
TXDATA[7:0],
TXPARITY
TXSOC
TXCLK
TXCLAV
TXEN
TXDATA[7:0],
TXPARITY
TXSOC
IDT77V106L25
In the transmit direction, the PHY first asserts TXCLAV (transmit cell
In the receive direction, RXEN indicates when the ATM device is prepared
Note that this Utopia interface can be operated in either cell-mode or in byte-
Figure 5. Utopia Transmit Handshake - Back to Back Cells and TXEN Suspended Transmission
P46
X
P47
H1
Figure 4. Utopia Transmit Handshake - Single Cell
H2
P48
P44
H1
9
complete cell. It will modulate TXCLAV to prevent the FIFO from overflowing.
Likewise, it may assert RXCLAV before a complete cell has been received,
and will modulate RXCLAV to prevent the FIFO from underflowing. There is
generally little advantage to the byte-mode, so most users will leave the
77V106L25 in the default cell-mode.
for one clock, coincident with the first byte of each cell. Odd parity is utilized
across each 8-bit data field, which means that for an all-zero pattern. the
corresponding parity bit is one.
The following figures show examples of the Utopia Level 1 handshake.
P45
In byte-mode, the phy can assert TXCLAV before it has room for a
In both transmit and receive, TXSOC and RXSOC (start of cell) is asserted
H2
P46
H3
P47
H4
P48
X
H5
X
77v106 drw 16
77v106 drw 17