IDT77V1254L25PG IDT, Integrated Device Technology Inc, IDT77V1254L25PG Datasheet - Page 27
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IDT77V1254L25PG
Manufacturer Part Number
IDT77V1254L25PG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT77V1254L25PG.pdf
(48 pages)
Specifications of IDT77V1254L25PG
Data Rate
25.6/51.2Mbps
Number Of Channels
4
Type Of Atm Phy Interface
DPI/UTOPIA
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
144
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT77V1254L25PGI
Manufacturer:
IDT
Quantity:
28
Company:
Part Number:
IDT77V1254L25PGI
Manufacturer:
IDT
Quantity:
621
Control and Status Interface
operating characteristics and functions, and to communicate status to external systems.
Enable (ALE) signal.
IDT77V1254L25
Utility Bus
The Utility Bus is a byte-wide interface that provides access to the registers within the IDT77V1254L25. These registers are used to select desired
The Utility Bus is implemented using a multiplexed address and data bus (AD[7:0]) where the register address is latched via the Address Latch
The Utility Bus interface is comprised of the following pins: AD[7:0], ALE, CS, RD, WR
Read Operation
Refer to the Utility Bus timing waveforms in Figures 43 and 44. A register read is performed as follows:
1. Initial condition:
2. Set up register address:
3. Read register data:
Write Operation
A register write is performed as described below:
1. Initial condition:
2. Set up register address:
3. Write data:
Interrupt Operations
P_TCLK
P_TFRM
P_TD(3:0)
– RD, WR, CS not asserted (logic 1)
– ALE not asserted (logic 0)
– place desired register address on AD[7:0]
– set ALE to logic 1;
–
– Remove register address data from AD[7:0]
– assert CS by setting to logic 0;
– assert RD by setting to logic 0
– wait minimum pulse width time (see AC specifications)
– RD, WR, CS not asserted (logic 1)
– ALE not asserted (logic 0)
– place desired register address on AD[7:0]
– set ALE to logic 1;
– latch this address by setting ALE to logic 0.
– place data on AD[7:0]
– assert CS by setting to logic 0;
– assert WR (logic 0) for minimum time (according to timing specification); reset WR to logic 1 to complete register write cycle.
latch this address by setting ALE to logic 0.
(out)
(in)
(in)
Nibble 104
Cell 1
Nibble 105
Cell 1
77V1254 Not Ready
ATM Layer Device Not Ready
Figure 30 DPI Transmit Handshake - Neither Device Ready
X
X
27 of 48
X
X
Nibble 0
Cell 2
Nibble 1
Cell 2
December 2004
Nibble 2
Cell 2
3505 drw 31
.