IDT77V1254L25PGI IDT, Integrated Device Technology Inc, IDT77V1254L25PGI Datasheet - Page 31

• Manufacturer Part Number: IDT77V1254L25PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1254L25PGI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 4
• Type Of Atm Phy Interface: DPI/UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

jitter measured at various data rates. The set-up shown in Figure 35 was used to perform these tests. The maximum jitter seen was at TX point 5 and
the minimum jitter was at point 2. The loop timing jitter is defined as the amount of jitter generated by each TX node. In other words, the loop timing
jitter or the jitter added by a loop-timed port in the set-up below is the difference between the Total Output Jitter and the Total Input Jitter.
derived. For example, at data rate of 25.6Mbps, jitter added going through Line Card 3 is 1.5ns -1.4ns (as shown in the waveforms below).
IDT77V1254L25
Jitter in Loop Timing Mode
One of the primary concerns when using loop timing mode is the amount of jitter that gets added each time data is transmitted. Table 3 shows the
Loop Timing Jitter Specification
The waveforms below show some of the measurements taken with the set-up in Figure 35. Using the formula above, the jitter specification was
OSC
Normal Mode
Line Rate
P0
Mbps
32
64
TX
RX
1
Figure 35 Test Setup for Loop Timing Jitter Measurements
Data Rate
Mbps
25.6
51.2
3
4
2
5
RX
TX
RX
RX
TX
TX
Table 3 Loop Timing Jitter
Loop Timing Mode
Loop Timing Mode
Loop Timing Mode
Min.
31 of 48
CLK
CLK
CLK
--
--
P1
P2
P3
100 ps
100 ps
Typ.
Data
Data
Data
Data
Data
Data
Max.
--
--
Using 32Mhz OSC
Using 64Mhz OSC
Note
SWITCH
December 2004