IDT77V1254L25PGI IDT, Integrated Device Technology Inc, IDT77V1254L25PGI Datasheet - Page 5

• Manufacturer Part Number: IDT77V1254L25PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1254L25PGI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 4
• Type Of Atm Phy Interface: DPI/UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Signal Descriptions
Signal Name
RX0+,-
RX1+,-
RX2+,-
RX3+,-
TX0+,-
TX1+,-
TX2+,-
TX3+,-
Signal Name
AD[7:0]
ALE
CS
RD
WR
Signal Name
DA
INT
MM
MODE[1:0]
OSC
RST
RXLED[3:0]
RXREF
SE
IDT77V1254L25
Pin Number
139, 138
133, 132
121, 120
115, 114
4, 3
144, 143
110, 109
106, 105
Pin Number
101, 100, 99, 98, 96, 95, 94,
93
91
90
89
88
Pin Number
103
85
6
7, 8
126
87
82, 81, 80, 79
9
102
I/O
In
In
In
In
Out
Out
Out
Out
I/O
In/Out Utility bus address/data bus. The address input is sampled on the falling edge of ALE. Data is output on this
In
In
In
I/O
In
Out
In
In
In
In
Out
Out
In
Port 0 positive and negative receive differential input pair.
Port 1 positive and negative receive differential input pair.
Port 2 positive and negative receive differential input pair.
Port 3 positive and negative receive differential input pair.
Port 0 positive and negative transmit differential output pair.
Port 1 positive and negative transmit differential output pair.
Port 2 positive and negative transmit differential output pair.
Port 3 positive and negative transmit differential output pair.
Utility bus address latch enable. Asynchronous input. An address on the AD bus is sampled on the falling
Utility bus asynchronous chip select. CS must be asserted to read or write an internal register. It may remain
Utility bus read enable. Active low asynchronous input. After latching an address, a read is performed by
Utility bus write enable. Active low asynchronous input. After latching an address, a write is performed by
Interrupt. INT is an open-drain output, driven low to indicate an interrupt. Once low, INT remains low until the
Mode Selects. They determine the configuration of the PHY/ATM interface. 00 = UTOPIA Level 2. 01 = UTO-
TTL line rate clock source, driven by a 100 ppm oscillator. 32 MHz for 25.6 Mbps; 64 MHz for 51.2 Mbps.
Reset. Active low asynchronous input resets all control logic, counters and FIFOs. A reset must be per-
Receive LED drivers. Driven low for 223 cycles of OSC, beginning with RXSOC when that port receives a
Reserved signal. This input must be connected to logic low.
Signal Description
Signal Description
bus when a read is performed. Input data is sampled at the completion of a write operation.
edge of ALE. ALE must be low when the AD bus is being used for data.
asserted at all times if desired
deasserting WR and asserting RD and CS.
deasserting RD, placing data on the AD bus, and asserting WR and CS. Data is sampled when WR or CS is
deasserted.
Signal Description
Reserved signal. This input must be connected to logic low.
interrupt status in the appropriate interrupt Status Register is read. Interrupt sources are programmable via
the interrupt Mask Registers.
Reserved signal. This input must be connected to logic low.
PIA Level 1. 10 = DPI. 11 is reserved.
formed after power up prior to normal operation of the part.
good (non-null and non-errored) cell. Drives 8 mA both high and low. One per port.
Receive Reference. Active low, synchronous to OSC. RXREF pulses low for a programmable number of
clock cycles when an x_8 command byte is received. Register 0x40 is programmed to indicate which port is
referenced.
Table 1 Signal Descriptions (Part 1 of 3)
Miscellaneous Signals
Utility Bus Signals
Line Side Signals
5 of 48
December 2004