MC33742DW Freescale, MC33742DW Datasheet - Page 56

• Manufacturer Part Number: MC33742DW
• Manufacturer: Freescale

Specifications of MC33742DW

• Data Rate: 1000Kbps
• Number Of Transceivers: 1
• Standard Supported: CAN 2.0
• Operating Supply Voltage (max): 27V
• Operating Supply Voltage (typ): 5/9/12/15/18/24V
• Operating Supply Voltage (min): 4.5V
• Package Type: SOIC W
• Supply Current: 45mA
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Not Compliant

INTERRUPT REGISTER (INTR)
source. A read operation identifies the interrupt source.
register content are copies of the IOR, CAN, TIM, and LPC registers status content. To clear the Interrupt Register bits, the IOR,
CAN, TIM, and/or LPC registers must be cleared (read register) and the recovery condition must occur. Errors bits are latched
in the CAN register and the IOR register.
Table 40. Interrupt Register
Table 41. Interrupt Register Control Bits
due to over-current detection (I
(not bit set into the INTR register).
Table 42. Interrupt Register Status Bits
56
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Notes
67.
68.
Tables 40
When the mask bit is set, the INT pin goes LOW if the appropriate condition occurs. Upon a wake-up condition from Stop mode
Reset Condition
Reset Value
If only HSOT - V2LOW interrupt is selected (only bit D2 set in INTR register), reading INTR register bit D2 leads to two possibilities:
1. Bit D2 = 1: Interrupt source is HSOT.
2. Bit D2 = 0: Interrupt source is V2LOW.
HSOT and V2LOW bits status are available in the IOR register.
See Table 13, page 47, for definitions of reset conditions.
(Write)
$111b
INTR
VSUPLOW
VDDTEMP
HSOT - V2LOW
HSOT
Name
CANF
VSUPLOW
through
(68)
VDDTEMP
Name
CANF
42
contain the Interrupt Register information. The INTR register allows masking or enabling the interrupt
R/W
W
R
–
–
DDS-WU1
Mask bit for CAN failures.
Mask bit for VDD medium temperature
(pre-warning).
Mask bit for HS over-temperature AND V
Mask bit for V
or I
Logic
POR, RST
VSUPLOW
VSUPLOW
DDS-WU2
0
1
0
1
0
1
0
1
D3
0
BF(EW)
), an INT pulse is generated; however, INTR register content remains at 0000
Table 42
< 5.8V.
No V
V
No HS over-temperature.
HS over-temperature.
No VDD medium temperature (pre-warning).
VDD medium temperature (pre-warning).
No CAN failure.
CAN failure.
BF(EW)
HSOT-V2LOW
BF(EW)
provides status bit information. The status bits of the INTR
POR, RST
< 5.8V.
HSOT
D2
0
< 5.8V.
2LTH
(67)
Description
< 4.0V.
Description
POR, RST
Analog Integrated Circuit Device Data
V1TEMP
V1TEMP
D1
0
Freescale Semiconductor
POR, RST
CANF
CANF
D0
0