TLE6266G Infineon Technologies, TLE6266G Datasheet - Page 18

• Manufacturer Part Number: TLE6266G
• Description: Network Controller & Processor ICs BODY SYSTEM ICS
• Manufacturer: Infineon Technologies

Specifications of TLE6266G

• Number Of Transceivers: 1
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (typ): 5V
• Package Type: DSO
• Operating Temperature (max): 150C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 28
• Product: Controller Area Network (CAN)
• Data Rate: 125 KBd
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.8 V
• Supply Current (max): 200 mA
• Maximum Operating Temperature: + 150 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: DSO
• Lead Free Status / RoHS Status: Not Compliant
• Other names: TLE6266GNT

Version 2.21
SPI CLK Monitoring during Cyclic Wake Mode
The TLE 6266 offers a feature to monitor the SPI clock signal (CLK pin) during the cyclic
wake mode. If there are edges on the CLK signal, the IC performs a reset and the RO
pin is set to LOW for t= t
again). This feature is activated if the CSN pin is set to HIGH.
6.8
The TLE 6266 has an internal oscillator with +/-15% accuracy. The typ. frequency of the
oscillator is 125kHz. After an internal 64-times frequency divider, this gives an typ. cycle
time t
the
activated via SPI input bit 3 and 4. During this test, the HS3-switch will be activated
cyclically.
6.9
When the output voltage V
RO is switched HIGH after a delay time t
microcontroller when the application is switched on. As soon as an under-voltage
condition of the output voltage (V
LOW again. The LOW signal is guaranteed down to an output voltage V
refer to Figure 17, reset timing diagram.
In the cyclic wake HS OFF mode, the watchdog circuit is automatically disabled.Both,
the undervoltage reset and the watchdog reset set all SPI input bits LOW.
Long Open Window
After the delayed reset (LOW to HIGH transition of RO) the window watchdog circuit is
started by opening a long open window. The long open window allows the
microcontroller to run his set-up and to trigger the watchdog via the SPI afterwards.
Within the long open window period a watchdog trigger is alternating detected as a
“rising” or “falling edge” by sampling a HIGH on the SPI input bit 0. The trigger is
accepted when the CSN input becomes HIGH after the transmission of the SPI word.
After every reset condition (watchdog reset, undervoltage reset) as well as a transition
from every mode into the cyclic wake HS ON mode, the watchdog starts the long open
window and the default value of the SPI input bit 0 is LOW.
Closed/Open Window
A correct watchdog trigger immediately results in starting the window watchdog by
opening the closed window followed by the open window (see Figure 18). From now on
the microcontroller has to service the watchdog trigger by inverting the SPI input bit 0
alternating. The “negative” or “positive” edge has to meet the open window time. A
correct watchdog service immediately results in starting the next closed window. Please
refer to Figure 19, watchdog timing diagram.
V
bat
cyc
= 0.512ms. The frequency of the oscillator can be measured within the normal,
stand-by and the RxD-only mode. This is a timebase test (see Chapter 6.15),
Oscillator
Window Watchdog and Reset
WDR
CC
(after t
exceeds the reset threshold voltage V
CC
WDR
< V
a long open window is started and RO is HIGH
RD
RT
18
. This is necessary for a defined start of the
) appears, the reset output RO is switched
Datasheet TLE 6266 G
RT
CC
the reset output
July 29th, 2005
1V. Please