DS25CP104ATSQ National Semiconductor, DS25CP104ATSQ Datasheet
DS25CP104ATSQ
Specifications of DS25CP104ATSQ
Available stocks
Related parts for DS25CP104ATSQ
DS25CP104ATSQ Summary of contents
Page 1
... Each differential input and output is internally terminated with a 100Ω resistor to lower return losses, reduce component count and further minimize board space. Typical Application © 2008 National Semiconductor Corporation Features ■ 3.125 Gbps low jitter, low skew, low power operation ■ ...
Page 2
... Ordering Code NSID Function DS25CP104ATSQ Crosspoint Switch Block Diagram www.national.com Available Equalization Available Pre-Emphasis Levels Off / Low / Medium / High Off / Low / Medium / High 30073601 2 Levels ...
Page 3
Connection Diagram DS25CP104A Pin Diagram 3 30073602 www.national.com ...
Page 4
Pin Descriptions Pin Name Pin Number IN0+, IN0 IN1+, IN1 IN2+, IN2 IN3+, IN3 OUT0+, OUT0-, 29, 28, OUT1+, OUT1-, 27, 26, OUT2+, OUT2-, 24, 23, OUT3+, OUT3- 22, 21 EQ0, ...
Page 5
... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage LVCMOS Input Voltage LVCMOS Output Voltage LVDS Input Voltage LVDS Differential Input Voltage LVDS Output Voltage LVDS Differential Output Voltage ...
Page 6
Symbol Parameter LVDS OUTPUT DC SPECIFICATIONS V Differential Output Voltage OD ΔV Change in Magnitude Output States V Offset Voltage OS ΔV Change in Magnitude Output States I Output Short Circuit Current ...
Page 7
AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 9, 10) Symbol Parameter LVDS OUTPUT AC SPECIFICATIONS (Note 11) t Differential Propagation Delay Low to PLHD High t Differential Propagation Delay High to PHLD Low ...
Page 8
Symbol Parameter JITTER PERFORMANCE WITH EQ = Off Low(Note 11) (Figure 6 Figure 9) t Random Jitter (RMS Value) RJ1A Test Channels A t RJ2A (Note 15) t Deterministic Jitter (Peak to Peak) DJ1A Test Channels A t ...
Page 9
Symbol Parameter JITTER PERFORMANCE WITH PE = Off Low (Note 11) (Figure 7 Figure 9) t Random Jitter (RMS Value) RJ1D Test Channels D t RJ2D (Note 15) t Deterministic Jitter (Peak to Peak) DJ1D Test Channels D ...
Page 10
Symbol Parameter SMBus AC SPECIFICATIONS f SMBus Operating Frequency SMB t Bus free time between Stop and Start BUF Conditions t Hold time after (Repeated) Start HD:SDA Condition. After this period, the first clock is generated. t Repeated Start Condition ...
Page 11
DC Test Circuits AC Test Circuits and Timing Diagrams FIGURE 1. Differential Driver DC Test Circuit FIGURE 2. Differential Driver AC Test Circuit FIGURE 3. Propagation Delay Timing Diagram FIGURE 4. LVDS Output Transition Times 11 30073620 30073621 30073622 30073623 ...
Page 12
Pre-Emphasis and Equalization Test Circuits www.national.com FIGURE 5. Jitter Performance Test Circuit FIGURE 6. Pre-Emphasis Performance Test Circuit FIGURE 7. Equalization Performance Test Circuit 12 30073629 30073627 30073626 ...
Page 13
FIGURE 8. Pre-Emphasis and Equalization Performance Test Circuit Test Channel Loss Characteristics The test channel was fabricated with Polyclad PCL-FR-370-Laminate/PCL-FRP-370 Prepreg materials (Dielectric constant of 3.7 and Loss Tangent of 0.02). The edge coupled differential striplines have the following geometries: ...
Page 14
Functional Description The DS25CP104A is a 3.125 Gbps 4x4 LVDS digital cross- point switch optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. The DS25CP104A operates in two modes: Pin Mode (EN_smb ...
Page 15
TABLE 3. Input Select Pins Configuration for the Output OUT2 S21 TABLE 4. Input Select Pins Configuration for the Output OUT3 S31 Setting Pre-Emphasis Levels The DS25CP104A has one PE level select ...
Page 16
DS25CP104A OPERATION IN THE SMBUS MODE The DS25CP104A operates as a slave on the System Man- agement Bus (SMBus) when the EN_smb pin is set to a high (1). Under these conditions, the SCL pin is a clock input while ...
Page 17
Register Descriptions There are five data registers in the DS25CP104A accessible via the SMBus interface. Address Name (hex) 0 Switch Configuration 1 PE Level Select 2 EQ Level Select 3 Control 4 LOS FIGURE 10. DS25CP104A Registers Block Diagram SWITCH ...
Page 18
PE LEVEL SELECT REGISTER The PE Level Select register selects the pre-emphasis level for each of the outputs. The following two tables show the register mapping and associated truth table. Bit Default Bit Name D[1: Level Select 0 ...
Page 19
CONTROL REGISTER The Control register enables SoftPWDN control, individual output power down (PWDNn) control, LOS Circuitry Enable control, PE Level Select Enable control and EQ Level Select Enable control via the SMBus. The following table shows the register mapping. Bit ...
Page 20
INPUT INTERFACING The DS25CP104A accepts differential signals and allows simple coupling. With a wide common mode range, the DS25CP104A can be DC-coupled with all common dif- Typical LVDS Driver DC-Coupled Interface to DS25CP104A Input Typical CML Driver ...
Page 21
OUTPUT INTERFACING The DS25CP104A outputs signals that are compliant to the LVDS standard. Its outputs can be DC-coupled to most com- mon differential receivers. The following figure illustrates typ- ical DC-coupled interface to common differential receivers Typical DS25CP104A Output DC-Coupled ...
Page 22
Typical Performance Characteristics Total Jitter as a Function of Data Rate Residual Jitter as a Function of Data Rate, FR4 Stripline Length and EQ Level Residual Jitter as a Function of Data Rate, FR4 Stripline Length and PE Level www.national.com ...
Page 23
Residual Jitter as a Function of Data Rate, FR4 Stripline Length and PE Level 30073655 Supply Current as a Function of Data Rate and PE Level 23 30073657 www.national.com ...
Page 24
Typical Performance A 2.5 Gbps NRZ PRBS-23 without PE After 30" Differential FR-4 Stripline DIV, V: 100 mV / DIV A 2.5 Gbps NRZ PRBS-23 with High PE After 2" Differential FR-4 Microstrip ...
Page 25
A 2.5 Gbps NRZ PRBS-23 without EQ After 60" Differential FR-4 Stripline DIV, V: 100 mV / DIV 30073668 A 2.5 Gbps NRZ PRBS-23 with High EQ After 60" Differential FR-4 Stripline ...
Page 26
... Physical Dimensions (See AN-1187 for PCB Design and Assembly Recommendations) www.national.com inches (millimeters) unless otherwise noted Order Number DS25CP104ATSQ NS Package Number SQA40A 26 ...
Page 27
Notes 27 www.national.com ...
Page 28
... For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock Conditioners www.national.com/timing Data Converters www.national.com/adc Displays www.national.com/displays Ethernet www.national.com/ethernet Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www ...