DS25CP104ATSQ National Semiconductor, DS25CP104ATSQ Datasheet - Page 10

• Manufacturer Part Number: DS25CP104ATSQ
• Manufacturer: National Semiconductor

Specifications of DS25CP104ATSQ

• Number Of Arrays: 1
• Differential Data Transmission: Yes
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Package Type: LLP EP
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Cascading Capability: No
• Line Code: NRZ
• On-chip Buffers: No
• On-chip Decoder: No
• On-chip Latch Circuit: No
• On-chip Mux/demux: No
• Programmable: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Input Level: CML/LVDS/LVPECL
• Output Level: LVDS
• Lead Free Status / RoHS Status: Supplier Unconfirmed

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SMBus AC SPECIFICATIONS
f
t
t
t
t
t
t
t
t
t
t
SMB
BUF
HD:SDA
SU:SDA
SU:SDO
HD:DAT
SU:DAT
TIMEOUT
LOW
HIGH
POR
Note 9: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 10: Typical values represent most likely parametric norms for V
product characterization and are not guaranteed.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: t
going edge of the same channel.
Note 13: t
all outputs).
Note 14: t
other within the operating temperature range.
Note 15: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Note 16: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted
algebraically.
Note 17: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
Symbol
SKD1
SKD2
SKD3
, |t
, Channel to Channel Skew, is the difference in propagation delay (t
, Part to Part Skew, is defined as the difference between the same signal path of any two devices running at the same V
PLHD
SMBus Operating Frequency
Bus free time between Stop and Start
Conditions
Hold time after (Repeated) Start
Condition. After this period, the first clock
is generated.
Repeated Start Condition setup time.
Stop Condition setup time
Data hold time
Data setup time
Detect clock low timeout
Clock low period
Clock high period
Time in which a device must be
operational after power-on reset
− t
PHLD
|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
Parameter
CC
= +3.3V and T
10
PLHD
A
or t
= +25°C, and at the Recommended Operation Conditions at the time of
Conditions
PHLD
) among all output channels in Broadcast mode (any one input to
Min
300
250
4.7
4.0
4.7
4.0
4.7
4.0
10
25
CC
Typ
and within 5°C of each
Max
100
500
35
50
Units
kHz
ms
ms
μs
μs
μs
μs
ns
ns
μs
μs