ZT8101 Intel (CPU), ZT8101 Datasheet - Page 40

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ZT8101

Manufacturer Part Number
ZT8101
Description
Manufacturer
Intel (CPU)
Datasheet

Specifications of ZT8101

Lead Free Status / RoHS Status
Supplier Unconfirmed
Miscellaneous Switch Features
8.3.1
8.3.2
8.4
40
Table 20. History Log Messages (Sheet 1 of 2)
System Memory Diagnostics
The PROM loader automatically runs the memory diagnostics each time the switch is booted. It is
divided into two parts. The first part tests the data bus and the second part tests the address bus.
Switch ASIC Diagnostics
The following are included in the switch’s ASIC level diagnostics.
History Log
The following table shows the message types and the messages that are currently supported in the
history log.
Device
Device
Device
Management
Management
Management
Management
Management
Direct Register Testing
Indirect Register Testing
Internal Buffers Testing
ARL L3 Table Testing
Port Based VLAN Table Testing
802.1Q Tagged VLAN Table Testing
Trunk Group Table Testing
Trunk Group Bitmap Table Testing
Inclusive Filter Mask Table Testing
Inclusive Filter Rules Table Testing
Layer 2 Multicast Table Testing
Default IP Router Table Testing
Layer 3 Interface Table Testing
External Buffers Testing
Layer 3 Multicast Table Testing
Type
Intel
®
NetStructure
System started up
Port 1: link up, 100 Mbps, full duplex
Port 1: link down
Successful log in through Telnet (Username: Edward)
Console session timed out (Username: Edward)
Login failed through Telnet (Username: Edward)
Successful log in through Telnet (Username: Edward)
Telnet session timed out (Username: Edward)
TM
ZT 8101 10/100 Ethernet Switch Technical Product Specification
Log Message

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