KSZ8864RMN Micrel Inc, KSZ8864RMN Datasheet - Page 95
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KSZ8864RMN
Manufacturer Part Number
KSZ8864RMN
Description
IC ETHERNET SW 4PORT 64QFN
Manufacturer
Micrel Inc
Datasheet
1.KSZ8864RMN.pdf
(112 pages)
Specifications of KSZ8864RMN
Controller Type
Ethernet Switch Controller
Interface
MII, RMII
Voltage - Supply
1.8V, 2.5V, 3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
*
Package / Case
*
Lead Free Status / RoHS Status
Supplier Unconfirmed
Current - Supply
-
Lead Free Status / RoHS Status
Supplier Unconfirmed, Lead free / RoHS Compliant
Other names
576-3787
KSZ8864RMN
KSZ8864RMN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
KSZ8864RMNI
Manufacturer:
MICREL
Quantity:
7 143
Company:
Part Number:
KSZ8864RMNUB
Manufacturer:
MICREL
Quantity:
101
January 2011
MIIM Registers
All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping
mechanisms used for MIIM and SPI. The “PHYAD” defined in KSZ8864RMN is assigned as “0x2” for port 1, “0x3” for
port 2. The “REGAD” supported are 0x0-0x5 (0h-5h), 0x1D (1dh) and 0x1F (1fh).
Address
Register 0h: MII Control
15
14
13
12
11
10
9
8
7
6
5
4
3
Name
Soft Reset
Loop Back
Force 100
AN Enable
Power Down
PHY Isolate
Restart AN
Force Full Duplex
Collision Test
Reserved
Hp_mdix
Force MDI
Disable Auto MDI/MDI-X
Description
1, Electrical PHY isolation of PHY from Tx+/Tx-.
Not supported.
1 = HP Auto MDI/MDI-X mode
1, PHY soft reset.
0, Normal operation.
1 = Perform MAC loopback, loop back path as follows:
Assume the loop-back is at port 1 MAC, port 2 is the
monitor port.
port 3, 4, 5
3, 4, 5 respectively
perform MAC loopback on port 3, 4, 5 respectively.
0 = Normal Operation.
1, 100Mbps.
0, 10Mbps.
1, Auto-negotiation enabled.
0, Auto-negotiation disabled.
1, Power down.
0, Normal operation.
0, Normal operation.
1, Restart Auto-negotiation.
0, Normal operation.
1, Full duplex.
0, Half duplex.
0 = Micrel Auto MDI/MDI-X mode
1, Force MDI.
0, Normal operation.
1, Disable auto MDI/MDI-X.
0, Normal operation.
Setting address ox3,4,5 reg. 0, bit 14 = ‘1’ will
Port 1 MAC Loopback (port 1 reg. 0, bit 14 = ‘1’)
Start: RXP2/RXM2 (port 2). Can also start from
Loopback: MAC/PHY interface of port 1’s MAC
End: TXP2/TXM2 (port 2). Can also end at port
95
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(SC)
RO
RO
M9999-012011-1.2
Default
0
0
1
1
0
0
0
0
0
0
1
0
0