KSZ8993M A5 Micrel Inc, KSZ8993M A5 Datasheet - Page 34
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KSZ8993M A5
Manufacturer Part Number
KSZ8993M A5
Description
Manufacturer
Micrel Inc
Datasheet
1.KSZ8993M_A5.pdf
(86 pages)
Specifications of KSZ8993M A5
Number Of Primary Switch Ports
3
Internal Memory Buffer Size
32
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Fiber Support
Yes
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII/SNI
Power Supply Type
Analog/Digital
Package Type
PQFP
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
1.89/3.465V
Operating Supply Voltage (min)
1.71/3.135V
Power Dissipation
800mW
Supply Current
0.1/0.19A
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Compliant
SMI register access is the same as the MIIM register access, except for the register access requirements
presented in this section.
Advanced Switch Functions
Spanning Tree Support
To support spanning tree, port 3 is the designated port for the processor.
The other ports (port 1 and port 2) can be configured in one of the five spanning tree states via “transmit enable”,
“receive enable” and “learning disable” register settings in registers 18 and 34 for ports 1 and 2, respectively. The
following description shows the port setting and software actions taken for each of the five spanning tree states.
Disable state:
Blocking state:
Listening state:
Learning state:
Micrel, Inc.
October 2008
Port setting:
Software action:
Port setting:
Software action:
Port setting:
Software action:
Port setting:
Registers are 8 data bits wide. For read operation, data bits [15:8] are read back as 0’s. For write
operation, data bits [15:8] are not defined, and hence can be set to either 0’s or 1’s.
“transmit enable = 0, receive enable = 0, learning disable =1”
“transmit enable = 0, receive enable = 0, learning disable =1”
“transmit enable = 0, receive enable = 0, learning disable =1”
“transmit enable = 0, receive enable = 0, learning disable = 0”
The processor should not send any packets to the port. The switch may still send specific packets
to the processor (packets that match some entries in the “static MAC table” with “overriding bit”
set) and the processor should discard those packets. Note: processor is connected to port 3 via
MII interface. Address learning is disabled on the port in this state.
The processor should not send any packets to the port(s) in this state. The processor should
program the “Static MAC table” with the entries that it needs to receive (e.g. BPDU packets). The
“overriding” bit should also be set so that the switch will forward those specific packets to the
processor. Address learning is disabled on the port in this state.
The processor should program the “Static MAC table” with the entries that it needs to receive
(e.g., BPDU packets). The “overriding” bit should be set so that the switch will forward those
specific packets to the processor. The processor may send packets to the port(s) in this state,
see “Special Tagging Mode” for details. Address learning is disabled on the port in this state.
The port should not forward or receive any packets.
Learning is disabled.
Only packets to the processor are forwarded.
Learning is disabled.
Only packets to and from the processor are forwarded.
Learning is disabled.
Only packets to and from the processor are forwarded.
Learning is enabled.
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M9999-020606
KSZ8993M/ML