PEF22558EV11GXP Lantiq, PEF22558EV11GXP Datasheet
PEF22558EV11GXP
Specifications of PEF22558EV11GXP
Related parts for PEF22558EV11GXP
PEF22558EV11GXP Summary of contents
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OctalFALC ...
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ABM , ACE , AOP , ARCOFI ® ® FALC , GEMINAX , IDEC ® ® MUSAC , MuSLIC , OCTAT ® ® SCOUT , SICAT , SICOFI ® ® 10BaseV , 10BaseVX 10BaseS™, EasyPort™, VDSLite™ are ...
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TM OctalFALC Revision History: Previous Version: Page Subjects (major changes since last revision) 46 Transmit Line Monitor 2005-05-03 Rev. 1.0 Rev. 2.0 wg_template_fm5_a5_2003-09-01.fm / DS4 ...
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... RCLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.5 DCO-R/DCO-X Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.6 PLL Reset and Configuring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.7 PLL Interrupt Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 Framer Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 Remote Defect Indication (E1 only 6.2 Automatic Sending of Transmit Remote Alarm (T1/J1 only 6.3 RSC Interrupt (T1/J1 only 6.4 DL-Bit Access (T1/J1 only CAS Features ...
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Table of Contents 10.4 Receive Line Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1 Overview Interface- and Basic Operation-Modes . . . . . . . . . . . . . . . . 11 Table 2 Intel Bus Interface Timing Parameter Values . . . . . ...
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Abstract This document describes the differences of PEF 22558 E, OctalFALC relative to the QuadFALC 1 General The number of receive and transmit channels has been increased from four to eight. All channels can be configured and used independently. To ...
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Receive RL1/RDIP/ROID(8:1) Line RL2/RDIN/RCLKI(8:1) Interface RLS(8:1) TDI Boundary TMS Scan TCK TRS Interface TDO XL1/XDOP/XIOD(8:1) Transmit XL2/XDON/XFM(8:1) Line XL3(8:1) Interface XL4(8:1) Figure 1 Logic Symbol 2.2 Software Compatibility TM The OctalFALC can be used in two basic modes. The “QuadFALC ...
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An overview is given in Table Additional features are available also in compatibility mode, but are disabled by default and must be activated by software. If compatibility mode is selected, the version status register VSTR shows the same value ® ...
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Table 1 Overview Interface- and Basic Operation-Modes Interface IM(1:0) COMP Mode Intel Motorola micro processor mode 0 SPI 10 Not valid SCI 11 In compatibility mode every global register exists one times in both of the pseudo ...
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Microcontroller Interface The microcontroller interface is selected if IM(1:0) is strapped to ´01 ´ (Motorola mode based on the existing QuadFALC acknowledge DTACK for Motorola- and READY for Intel-mode) is provided indicating successful read or write ...
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READY Figure 4 Intel Write Cycle Timing Ax BHE 4 ALE Figure 5 Intel Multiplexed Address Timing Delta Sheet OctalFALC ...
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Ax BHE Figure 6 Intel Non Multiplexed Address Timing Table 2 Intel Bus Interface Timing Parameter Values No. Parameter 1 Address, BHE setup time 2 Address, BHE hold time 3 CS setup time 3A CS hold time ...
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Table 2 Intel Bus Interface Timing Parameter Values (cont’d) No. Parameter delay after READY 31 READY hold time after Data stable before READY READY delay READY ...
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Ax, BLE DTACK Figure 8 Motorola Write Cycle Timing Table 3 Motorola Bus Interface Timing Parameter Values No. Parameter 17 Address, BLE setup time before DS active 18 Address, BLE hold after DS inactive 19 CS ...
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Table 3 Motorola Bus Interface Timing Parameter Values (cont’d) No. Parameter 25 Data hold after DS inactive (read access) 26 Data stable before DS active (write access) 27 Data hold after DS inactive (write access delay after DTACK ...
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DSTR so long as it read no longer the value ´F 4.1 SCI Interface The Serial Control Interface (SCI) is selected if IM(1:0) is strapped to ´11 The ...
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Microprocessor Interworking Figure 9 SCI interface Application with Point to Point Connections Micro-processor or Interworking Device Figure 10 SCI interface Application with Multipoint to Multipoint Connection The following configurations of the SCI interface of the OctalFALC microcontroller by a write ...
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The following SCI configurations are fixed and cannot be set by the microcontroller: – Interrupt feature is disabled, bit INT_EN = ´0 – Arbitration always made with LAPD (only SCI applications like in Figure 10 are possible), bit ARB = ...
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SCI configuration register addresses. Because of the address space of the TM OctalFALC , really 11 LSBs of the 14 bit address are used in the OctalFALC MSBs are ignored. The Frame Check Sequence FCS has16 bits. The ...
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Source CMD Address Source address Source ACK Address Figure 13 Principle of Building of Addresses and RSTA Bytes in the SCI ACK Message Read Status Byte (RSTA) of the Acknowledge (ACK) 7 (MSB) 6 VFR RDO Field Bits Description VFR ...
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Field Bits Description SA(1:0), [3:0] Reserved C/R, TA Table 4 Definition of Control Bits in Commands (CMD) Control Bits (MSB LSB Table 5 SCI Configuration Register Content Address bit 7 bit 6 (MSB) ´0000 ´ PP ...
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Table 6 SCI Timing Parameter Values No Parameter 1 SCI_CLK cycle time full duplex mode 1 SCI_CLK cycle time half duplex mode 2 SCI_CLK low time 3 SCI_CLK high time 4 SCI_RXD setup time before SCI_CLK 5 SCI_RXD hold time ...
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CS SCLK SDI high impedance SDO Figure 15 SPI Read Operation CS SCLK SDI high impedance SDO Figure 16 SPI Write Operation Delta Sheet A10 11 bit address A10 11 bit address ...
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CS 1 SCLK 4 3 SDI high impedance SDO Figure 17 SPI Interface Timing Table 7 SPI Interface Timing Parameter Values No. Parameter - SCLK frequency 1 CS setup time before SCLK 2 CS hold time after SCLK 3 SDI ...
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Clock Modes 5.1 Individual Receive Clock Selection The source of every of the eight receive clocks (RCLK(8:1)) can be independently selected out of every of the eight channels. The additional registers GPC2 to GPC6 are used for controlling. GPC2 ...
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TCLK loss is detected if the transmit clock derived from TCLK failed to occur. Automatic transmit clock switching is controlled by the register bit CMR4.ATCS. If the TCLK input is used directly as transmit clock XCLK, the output of the ...
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The appropriate P- and I- factors of the PLL loop filter and registerbits of CMR3 and CMR6 are to be ...
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GCM(8:1) accordingly, see formulas in GCM6 description. All eight ports can work mode individually. After reset the clocking unit is in “flexible master clocking mode”. • In the “clocking fixed mode” (GCM2.VFREQ_EN = ´0´) the ...
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MCLK must be active and must have a defined frequency before reset becomes inactive. Depending on the supplied MCLK frequency the internal PLL must be configured if the SCI- or SPI-Interface mode is selected by IM(1:0). ...
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Table 8 Conditions for a PLL Reset (cont’d) Reset Pin GCM2.VFREQ_EN inactive 5.7 PLL Interrupt Status Bits If the central clock PLL status indication bit GIS2.PLLLS changes, an interrupt is generated. An additional bit GIS2.PLLLC is provided to indicate the ...
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... Automatic Sending of Transmit Remote Alarm (T1/J1 only) Note FALC56 V2 In T1/J1 mode, the Automatic Remote Alarm feature (AXRA) is now compliant with ANSI T1.403-1999 (see fulfilled.) Delta Sheet Figure 21).(The one-second requirement for on/off must OctalFALC PEF 22558 E Framer Features Rev. 2.0, 2005-05-03 ...
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... BOM code) That´s another ordering as in ANSI T1.403, 1999, table 4 !!. Sending is done as for HDLC: LSB first. That´s consistent to the note 1) in the ANSI: “rightmost bit transmitted first”. Delta Sheet Figure 22 and Figure 23. The optional mode 34 TM OctalFALC PEF 22558 E Framer Features Rev. 2.0, 2005-05-03 ...
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... DL7 DL5 DL5 DL3 DL1 DL23 DL21 DL21 DL19 DL17 DL15 DL13 . . . 35 OctalFALC PEF 22558 E Framer Features LSB Interrupts DL3 DL1 RDL1, 1st read DL19 DL17 RDL2, 1st read DL3 DL1 RDL1, 2nd read DL19 DL17 RDL2, 2nd read DL3 DL1 ...
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CAS Features 7.1 Basic CAS Operation Mode The basic operation mode (serial or register based) can be selected individually for receive and transmit direction. If RSIG is configured on one of the RX multifunction ports RPA...RPC, serial RX-CAS data ...
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HDLC/BOM Controllers Each of the eight ports provides three HDLC/BOM Controllers. Each of these units can be attached to either the line side (“standard”) or the system side (“inverse”). Inverse HDLC mode is selected by setting MODE.HDLCI = 1, ...
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Table 9 Receive FIFO User Depth (HDLC channel 1) and Bit Positions in Register RBCL # bytes CCR1.RFT(1: Receive Line Receive Interface Buffer 1...8 Transmit Line Transmit Interface Buffer 1...8 ...
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Switchin between HDLC and BOM (if both MODE.BRAC and MODE.HRAC are set) will be done in the following way: • After reset the HDLC/BOM controller is in HDLC mode • After eight consecutive ones (´FF that eight consecutive ones are ...
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OctalFALC Pseudo QuadFALC 1 RDO1 8 MHz; 4-to-1 multiplex mode Pseudo QuadFALC 2 RDO5 8 MHz; 4-to-1 multiplex mode compatible to QuadFALC Figure 26 Principle of System Interface Multiplex Modes, shown for RDO Table 10 System Multiplex Modes GPC1.SMM GPC6:SSI16 ...
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Clock Edge Selection The active clock edge of SYPX can be selected related to that of the other interface transmit data and marker. Also selection of the clock edge for SYPR is possible related to that of the other ...
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Redundancy Mode In redundancy mode the data inputs XDI are connected together. The outputs RDO and the signaling outputs RSIG (if used) of two channels can be connect together in the TM OctalFALC also, because one of them is ...
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Table 12 Redundancy Application Using RLM Mode (cont’d) Configuration Receive system interface SIC3.RRTRI RLM mode E1/T1/J1 Transmit Line E1/T1/J1 Receive Line Figure 27 Redundancy Application (shown for one channel and using RLM) To fulfill these requirements the RX- and TX-pathes ...
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E1/T1/J1 Transmit Line E1/T1/J1 Receive Line Figure 28 Long Haul Redundancy Application using the Analog Switch (shown for one line) Table 13 Redundancy Application Using the Analog Switch, Switching with only one Board Signal Configuration XLT, XLT RTDMT Receive system ...
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Line Interface 10.1 Tunable Transmit Line Output Resistance For optimized return loss the transmit output resistance can be configured by using the pins XL3 and XL4 as shown in Generic E1/T1/J1 applications can be built where the operation mode ...
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Transmit Line Monitor Shorts between XL1 and XL2 cannot be detected. A short between XL1 and XL2 will not ham the device. 10.3 Programmable Pulse Shaper and Line Build-Out The transmitter includes a programmable pulse shaper to generate transmit ...
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Table 15 Recommended Pulse Shaper Programming for T1/J1 with registers XPM(2:0) (Compatible to QuadFALC LBO Range Range [dB] [m] [ft 133 133 to 266 122 266 to ...
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The pulse shape configuration will be done also by the registers TXP(16:1) if LBO attenuation is selected. The pulse shape is then determined by both the values of TXP(16:1) and the LBO filtering. The given values in the following tables ...
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Receive Line Termination In general the E1 line impedance operating modes with 75 or with 120 (used with twisted pair cable) line termination are selectable by switching resistors in parallel or using special transformers with different transfer ratios in ...
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Table 19 Receiver Configuration Examples Line External Impeance Resistor 120 100 (for common 100 E1/T1/J1 applications) 75 Delta Sheet External Inter- Resistor R nal E1 E2 Ana- log Switc h 300 (for off common off E1/T1/J1 applications) ...
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Multi Function Port Features Several additional functions are available on the multi function ports, see features known from QuadFALC selected (SYPR or SYPX) with exception of the ports RPC were RCLK output is selected: The register bits PC3.RPC2 have ...
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Table 20 Multi Function Port Selection (cont’d) Selec- RFP Avail. RFP Function tion Signal 0101 DLR ABC 0110 FREEZE ABC 0111 RFSP ABC 1000 RLT ABC 1001 GPI ABC 1010 GPOH ABC 1011 GPOL ABC 1100 LOS ABC 1101 RTDMT ...
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Test and Maintenance 12.1 PRBS Test Signal Different PRBS modes which are using different bits and time slots in a E1/T1/J1 frame can be selected, see Table In the so called “unframed” mode all bits of all slots in ...
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Note that this mode can be used also in E1 mode, but makes no sense CAS disturbance can be avoided by deselection of the appropriate time slot 16. Note that the “N 56 kbit/s” mode is automatically ...
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Table 21 Supported PRBS Polynomials (pattern) (cont’d) TPC0.PRP TPC0.PRM Table 22 Bit/Timeslot Selection of PRBS Pattern TPC0.PRM TPC0.FRA 12.2 PPR Enhancement (T1/J1 only) The PPR (Periodical ...
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Automatic loop switching must be enabled through configuration register bits ALS.SILS for the In-Band Loop codes coming from the system side and ALS.LILS for the In-Band Loop codes coming from the line side respecively. Automatic loop switching is logically ored ...
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Note: 1. For SF format the protocoll currently used by the carriers for network access to the customer installation (CI in-band control code. Note that E1/T1repeaters are in general transparent, so they have not any influence on the ...
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Table 23 Out-Band Loop (BOM) Messages Function line loopback activate line loopback deactivate payload loopback activate payload loopback deactivate universal loopback deactivate 12.4.1 Bit Oriented Messages (BOM): Generation, Detection and Loop Switching (T1/J1) TM The OctalFALC performes the following functionalities ...
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If ALS.SOLS is set, the payload loop is activated after the “payload loopback activate“ code was detected from the line side or the system side and if the local loop is not activated by LIM0.LL = ´1´. The payload loop ...
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BOM messages coming from the system side can be detected. BOM messages coming from the system side are not included in (ANSI-)standards, but can be handled by ...
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Supported Standards The following international standards are supported additionally by this device: • ANSI T1.231 • ITU-T G.812 • ITU-T G.733 • ITU-T JG.733 • JEDECJ-STD-020A-1999-04 • JEDECJ-STD-020B-1999-07 14 Development Support 14.1 IBIS Model A new IBIS model is ...
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QuadFALC V2.1: CIS (global) PLLL GIS (per channel) OctalFALC V1.1, COMP=1: CIS (A10=CS2=1; CS1=0) PLLL CIS (A10=CS2=0; CS1=1) PLLL GIS (A10=CS2=x) OctalFALC V1.1, COMP=0: CIS (A10=x) GIS8 GIS7 GIS6 GIS5 GIS (A10=x) ISR7 GIS2 (A10=x) Figure 31 GIS Register Compatibility ...
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QuadFALC V2.1: VSTR OctalFALC V1.1, COMP=1: VSTR (A10=CS2=1; CS1=0) DSTR (A10=CS2=1; CS1=0) VSTR (A10=CS2=0; CS1=1) DSTR (A10=CS2=0; CS1=1) OctalFALC V1.1, COMP=0: VSTR (A10=x) DSTR (A10=x) Figure 32 VSTR and DSTR Register Compatibility 15.2 Pseudo QuadFALC The register GPC1 (global port ...
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A(9:0) GPC1, address 85 CS1 Pseudo QuadFALC 1 GPC1, address 85 CS2 Pseudo QuadFALC 2 GPC1, address 85 A(10:0) GPC2, address 008A Figure 33 Principle of configuration of SEC/FSC Output The 2:1 multiplexer is controlled by the register bits GPC1.CSFP(1:0) ...
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Table 25 Overview of Additional Control Register Functions for E1 Mode Register Short Name MODE_E IPC_E CCR2_E RDICR_E IMR3_E IMR4_E IMR5_E IMR6_E XPM2_E SIC4_E LIM0_E SIC3_E CMR4_E CMR5_E CMR6_E CMR1_E CMR2_E CMR3_E PC1_E PC2_E PC3_E PC5_E GPC1_E PC6_E CMDR3_E CMDR4_E ...
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Table 25 Overview of Additional Control Register Functions for E1 Mode Register Short Name MODE2_E MODE3_E GCM2_E GCM4_E XFIFO2L_E XFIFO2H_E XFIFO3L_E XFIFO3H_E TSE0_E TSBS2_E TSBS3_E TSS2_E TSS3_E GIMR_E TPC0_E TXP1_E TXP2_E TXP3_E TXP4_E TXP5_E TXP6_E TXP7_E TXP8_E TXP9_E TXP10_E TXP11_E ...
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Table 25 Overview of Additional Control Register Functions for E1 Mode Register Short Name TXP16_E GPC3_E GPC4_E GPC5_E GPC6_E INBLDTR_E ALS_E PRBSTS1_E PRBSTS2_E PRBSTS3_E PRBSTS4_E IMR7_E Table 26 Overview of Additional Status Register Functions for E1 Mode Offset Register Short ...
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... Interrupt Port Configuration Common Configuration Register 1 Common Configuration Register 2 Interrupt Mask Register 3 Interrupt Mask Register 4 Interrupt Mask Register 5 Interrupt Mask Register 6 Framer Mode Register 5 Transmit Control 0 Transmit Pulse-Mask Register 2 System Interface Control 4 Line Interface Mode 0 System Interface Control 3 Clock Mode Register 4 ...
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Table 27 Overview of Additional Control Register Functions for T1/J1 (cont’d) Register Short Name PC4_T PC5_T GPC1_T PC6_T CMDR3_T CMDR4_T GPC2_T CCR3_T CCR4_T MODE2_T MODE3_T GCM2_T GCM4_T XFIFO2L_T XFIFO2H_T XFIFO3L_T XFIFO3H_T TSE0_T TSBS2_T TSBS3_T TSS2_T TSS3_T GIMR_T TPC0_T TXP1_T TXP2_T ...
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Table 27 Overview of Additional Control Register Functions for T1/J1 (cont’d) Register Short Name TXP7_T TXP8_T TXP9_T TXP10_T TXP11_T TXP12_T TXP13_T TXP14_T TXP15_T TXP16_T GPC3_T GPC4_T GPC5_T GPC6_T INBLDTR_T ALS_T PRBSTS1_T PRBSTS2_T PRBSTS3_T PRBSTS4_T IIMR7_T Table 28 Overview of Additional ...
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Table 28 Overview of Additional Status Register Functions for T1/J1s (cont’d) Register Short Name Register Long Name SIS3_T Signaling Status Register 3 RSIS3_T Receive Signaling Status Register 3 RFIFO2L_T Receive FIFO 2 Lower Byte RFIFO2H_T Receive FIFO 2 Higher Byte ...
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External Signals In addition to the signals known from QuadFALC provided. The logic symbol is shown in A signal list is given in Table Only additional signals or signals with extended functions against the ® QuadFALC V2.1 are listed. ...
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Table 29 I/O Signals (cont’d) Pin No. Ball Name No. - 15T RL2.6 RDIN6 RCLKI6 - 14T RLS26 - 13A RL1.7 RDIP7 ROID7 - 15A RL2.7 RDIN7 RCLKI7 - 14A RLS27 - 11A RL1.8 RDIP8 ROID8 - 10A RL2.8 RDIN8 ...
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Table 29 I/O Signals (cont’d) Pin No. Ball Name No XL3 XL4 XL3 XL4.4 - 11N XL1.5 XDOP5 XOID5 - 10N XL2.5 XDON5 XFM5 - 11P XL3.5 - 10P XL4.5 - 14N ...
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Table 29 I/O Signals (cont’d) Pin No. Ball Name No. - 14D XL1.7 XDOP7 XOID7 - 13D XL2.7 XDON7 XFM7 - 14C XL3.7 - 13C XL4.7 - 11E XL1.8 XDOP8 XOID8 - 10E XL2.8 XDON8 XFM8 - 11D XL3.8 - ...
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Table 29 I/O Signals (cont’d) Pin No. Ball Name No COMP - 6B IM1 - 4B IM0 Delta Sheet Pin Buffer Function Type Type I PU Software Compatibility Mode 1 QuadFALC B (“Compatibility Mode”) is selected: OctalFALC used ...
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Table 29 I/O Signals (cont’d) Pin No. Ball Name No. Microprocessor and Serial Interfaces - K12 A10 CS2 - J12 J15 J16 J14 J13 A1 A1 Delta Sheet ...
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Table 29 I/O Signals (cont’d) Pin No. Ball Name No. - G16 D15 PLL10 - 2F D14 PLL9 - 3F D13 PLL8 - 4F D12 PLL7 - 1G D11 PLL6 - 2G D10 PLL5 - 3G ...
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Table 29 I/O Signals (cont’d) Pin No. Ball Name No PLL3 - 2H D7 PLL2 - 1J D6 PLL1 - 3H D5 PLL0 - 3K D2 SCI_CLK SCLK - 1K D1 SCI_RXD SDI - 2K D0 SCI_TXD ...
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Table 29 I/O Signals (cont’d) Pin No. Ball Name No. - 12H CS CS1 - 11H INT INT1 - 14H INT2 14G READY DTACK Clock Signals - 16P SCLKR5 - 16M SCLKR6 - 13F SCLKR7 - 16E SCLKR8 - 12M ...
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Table 29 I/O Signals (cont’d) Pin No. Ball Name No. - 10M RDO6 - 15F RDO7 - 13E RDO8 - 11M XDI5 - 14L XDI6 - 9F XDI7 - 15C XDI8 Multifunction Ports - 1B RPA1 - 2D RPB1 - ...
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Table 29 I/O Signals (cont’d) Pin No. Ball Name No. - 15D RPB8 - 11F RPC8 - 3E XPA1 - 2E XPB1 - 5F XPA2 - 6F XPB2 - 7L XPA3 - 2M XPB3 - 1P XPA4 - 1R XPB4 ...
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Table 30 Pinstrapping Overview (cont’d) Pin Used A(10) only in micro controller interface modes A(5:0) only in SCI interface mode D(15:5) only in SCI or SPI interface mode 17 Package Due to the increased number of signals, a PG-LBGA-256-1 package ...
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A16 C 0.2 Figure 34 PG-LBGA-256-1 (Plastic Green Low Profile Ball Grid Array Package) Delta Sheet 256x ø0.5 ±0.1 ø0. ø0 ±0 OctalFALC PEF 22558 E Package Index Marking A1 T1 ...
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Electrical Characteristics This chapter describes operating conditions and DC characteristics and limits. 18.1 Absolute Maximum Ratings Table 31 defines the maximum voltages and temperature which may be applied to the device without damage. Table 31 Absolute Maximum Ratings Parameter ...
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Table 31 Absolute Maximum Ratings (cont’d) Parameter ESD robustness HBM ESD robustness CDM Attention: Absolute Maximum Ratings are stress ratings only, and functional operation and reliability under conditions beyond those defined in the normal operating conditions is not guaranteed. Stresses ...
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Table 32 Operating Range (cont’d) Parameter Digital input voltages Ground 1) Voltage ripple on analog supply less than Note: , and DD DDR DDX 18.3 DC Characteristics Table 33 DC Characteristics Parameter Input low voltage ...
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Table 33 DC Characteristics (cont’d) Parameter Average power supply current (digital line interface mode, single power supply) Input leakage current Input leakage current Input pullup current Output leakage current Transmitter leakage current Transmitter output impedance Transmitter output current Differential peak ...
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Table 33 DC Characteristics (cont’d) Parameter Receiver input impedance Receiver sensitivity 1) Applies to all input pins except analog pins RLx 2) Applies to all output pins except pins XLx 3) System interface at 16 MHz; all-ones data. 4) Pin ...
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Published by Infineon Technologies AG ...