ADM6996L-AA-T-1 Lantiq, ADM6996L-AA-T-1 Datasheet
ADM6996L-AA-T-1
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ADM6996L-AA-T-1 Summary of contents
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... ADM6996L/LX 6 Port Ethernet Switch Controller Revision History: 2005-11-22, Rev. 1.13 Previous Version: 1.05 Page/Date Changed to the new Infineon format Sept./2004 Rev. 1.1 changed to Rev. 1.11 Oct./2005 Rev. 1.11 changed to Rev. 1.12 for fixing pin type on page 15 Nov./2005 Revision 1.12 changed to Revision 1.13 Minor change ...
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... Automatic Link Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11 Clock Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 Auto Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13 Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.15 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.15.1 Address Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.15.2 Address Recognition and Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15.3 Address Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15.4 Back off Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Data Sheet 3 ADM6996L/LX Data Sheet Rev. 1.13, 2005-11-22 ...
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... MII Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.4 10Base-TX MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.5 100Base-Tx MII Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.6 100Base-TX MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.7 GPSI(7-wire) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.8 GPSI (7-wire) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.1 128 Pin PQFP Outside Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Data Sheet 4 ADM6996L/LX Data Sheet Rev. 1.13, 2005-11-22 ...
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... ADM6996L/LX Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2 5 TP/FX PORT + 1 MII PORT 128 Pin Diagram Figure 3 LED Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 4 ADM6996L/LX Serial Chip’s Internal Counter or EEPROM Access Timing . . . . . . . . . . . . . . . . . . 55 Figure 5 ADM6996L/LX Issue Reset Internal Counter Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 6 TP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 7 Fx Interface Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 8 Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 9 EEPROM Interface Timing ...
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... EEPROM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 31 10Base-Tx MII Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 32 10Base-TX MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 33 100Base-TX MII Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 34 100Base-TX MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 35 GPSI (7-wire) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 36 GPSI (7-wire) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Data Sheet 6 ADM6996L/LX Data Sheet Rev. 1.13, 2005-11-22 ...
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... Full-Duplex mode to prevent packet lost when buffer full. When Back Pressure is enabled, and there is no receive buffer available for the incoming packet, the ADM6996L/LX will issue a JAM pattern on the receiving port in Half Duplex mode and transmit the 802.3x Pause packet back to receiving end in Full Duplex mode. ...
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... Applications ADM6996L/LX in 128-pin PQFP: SOHO 5-port switch 5-port switch + Router with MII CPU interface. 1.4 Block Diagram Figure 1 below shows a simple block diagram of the ADM6996L/LX internal blocks. Addr Table 2K Entry Packet Buffer Figure 1 ADM6996L/LX Block Diagram Data Sheet MII/GPSI Address ...
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... GNDA 126 RXP0 127 RXN0 128 VCCAD Figure 2 5 TP/FX PORT + 1 MII PORT 128 Pin Diagram 2.2 Pin Description by Function ADM6996L/LX pins are categorized into one of the following groups: Data Sheet ADM6996L 9 ADM6996L/LX Data Sheet Interface Description 64 GNDIK 63 (GFCEN) TXD0 62 ...
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... Acts as MII transmit data TXD[0]. Synchronous to the rising edge of TXCLK. I/O 8mA Global Flow Control Enable PU At power-on-reset, latched as Full Duplex Flow control setting“1” to enable flow-control (default), “0” to disable flow-control. 10 ADM6996L/LX Data Sheet Interface Description Rev. 1.13, 2005-11-22 ...
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... MII Port Collision input /GPSI Collision Input Internal pull down MII Port Carrier Sense /GPSI Carrier Sense Internal pull down MII Port Receive Clock Input /GPSI RXCLK I PD MII Port Transmit clock Input /GPSI TXCLK 11 ADM6996L/LX Data Sheet Interface Description Rev. 1.13, 2005-11-22 ...
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... Active low“1” for half-duplex and “blinking” for collision indication“0” for full-duplex indication O 8mA Duplex/Collision LED4 Active low“1” for half-duplex and “blinking” for collision indication“0” for full-duplex indication 12 ADM6996L/LX Data Sheet Interface Description Rev. 1.13, 2005-11-22 ...
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... Used to indicate corresponding port’s speed status 100Mb 10Mb 8mA Speed LED[4:0]. Used to indicate corresponding port’s speed status 100Mb 10Mb 8mA Speed LED[4:0]. Used to indicate corresponding port’s speed status 100Mb 10Mb ADM6996L/LX Data Sheet Interface Description Rev. 1.13, 2005-11-22 ...
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... LED.“1” to set Dual Color mode for LED. Pin Buffer Function Type Type Block Ground I - Power Used by Tx Line Driver, 1 Power Used by AD Block, 3 Bias Block Ground I - Bias Block Power I - PLL Ground I - PLL Power, 1 Digital Core Ground I - Digital Core Power, 1 ADM6996L/LX Data Sheet Interface Description Rev. 1.13, 2005-11-22 ...
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... Crystal Input. Variation is limited to +/- 50ppm. AO Analog 25M Crystal Output. When the device is connected to an oscillator, this pin should be left unconnected. I TTL CFG0 Must be connected to GND. I TTL TEST Value. For normal applications connect to GND ADM6996L/LX Data Sheet Interface Description Rev. 1.13, 2005-11-22 ...
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... Receiver The 100Base-X receiver consists of functional blocks required to recover and condition the 125Mbits/s receive data stream. The ADM6996L/LX implements the 100Base-X receiving state machine diagram as given in the ANSI/IEEE Standard 802.3u, Clause 24. The 125Mbits/s receive data stream may originate from the on-chip twisted-pair transceiver in a 100Base-TX application ...
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... Symbol Alignment The symbol alignment circuit in the ADM6996L/LX determines code word alignment by recognizing the /J/K delimiter pair. This circuit operates on unaligned data from the de-scrambler. Once the /J/K symbol pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary. ...
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... If this condition is detected, then the ADM6996L/LX will assert RXER and present RXD[3:0] = 1110 to the internal MII for the cycles that correspond to received 5B code-groups until at least two idle code-groups are detected. ...
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... Transmit Driver and Receiver The ADM6996L/LX integrates all the required signal conditioning functions in its 10Base-T block such that external filters are not required. Only one isolation transformer and impedance matching resistors are needed for the 10Base-T transmit and receive interface. The internal transmit filtering ensures that all the harmonics in the transmission signal are attenuated properly ...
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... Jabber Function The jabber function monitors the ADM6996L/LX output and disables the transmitter if it attempts to transmit a longer than legal sized packet. If TXEN is high for greater than 24ms, the 10Base-T transmitter will be disabled. Once disabled by the jabber function, the transmitter stays disabled for the entire time that the TXEN signal is asserted ...
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... Address Learning The ADM6996L/LX uses a hash algorithm to learn the MAC address and can learn MAC addresses. An address is stored in the Address Table. The ADM6996L/LX searches for the Source Address (SA incoming packet in the Address Table and acts as below: ...
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... If the SA was not found in the Address Table (a new address), the ADM6996L/LX waits until the end of the packet (non-error packet) and updates the Address Table. If the SA was found in the Address Table, then the aging value of each corresponding entry will be reset When the DA is PAUSE command, then the learning process will be disabled automatically by ADM6996L/LX. ...
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... Full Duplex Flow Control When full duplex port run out of its receive buffer, a PAUSE packet command will be issued by ADM6996L/LX to notice the packet sender to pause transmission. This frame based flow control is totally compliant to IEEE 802.3x. ADM6996L/LX can issue or receive pause packet. ...
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... Example2: Port receives Untag packet and send to Tag port. ADM6996L/LX will check the port user define fours bits of VLAN ID first then check VLAN group resister. If destination port same VLAN as receiving port than this packet will forward to destination port with four byte VLAN Tag and new CRC ...
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... LED-High Link/Act Figure 3 LED Display Data Sheet Single Color R? 510 Dual Color Mode R? 510 D? LED D? LED 25 ADM6996L/LX Function Description Mode D? VCC LED Speed Rev. 1.13, 2005-11-22 Data Sheet ...
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... PHY Restart ConfigReg_ Miscellaneous Configuration Register 9 BWCon_0 Bandwidth Control Register 0 BWCon_1 Bandwidth Control Register 1 BWConEn Bandwidth Control Enable Register The register is addressed wordwise. Data Sheet Registers DescriptionEEPROM Content End Address Note 33 H Offset Address ADM6996L/LX Data Sheet Page Number Rev. 1.13, 2005-11-22 ...
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... SW can read the register, with write mask the register can be cleared SW can read and write this register Register is read and writable by SW Writing to the register generates a strobe signal for the HW (1 pdi clock cycle) Register is read and writable by SW. Description 27 ADM6996L/LX Data Sheet Rev. 1.13, 2005-11-22 ...
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... Signature 15:0 ro Note: ADM6996L/LX will check register 0 value before read all EEPROM content. If this value not match with 0x4154h then other values in EEPROM will be useless. ADM6996L/LX will use internal default value. User cannot write Signature register when programming ADM6996L/LX internal register. ...
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... Operating Speed 0 10, 10Mbps B 1 100, 100 Mbps B Auto-negotiation 0 D, Disable Enable B 802.x Flow Control Command 0 D, Disable Enable B Offset 0A H Description Reserved Replace Packet Not replaced Replaced with 1 by PVID B Reserved 29 ADM6996L/LX Data Sheet Reset Value 0040F H Rev. 1.13, 2005-11-22 ...
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... Reserved Trunk Enable 0 D, Disable Port 3 and Enable Port 3 and 4 B Inter Packet Gap Setting 0 96B, 96 bits B 1 92B, 92 bits B Reserved Offset 0C H Description Reserved Offset ADM6996L/LX Data Sheet Reset Value 040F H Reset Value 040F H Reset Value 040F H Rev. 1.13, 2005-11-22 ...
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... Type of Service (TOS) Priority Map Register Sets TOS priority TOS_Priority TOS priority Map Register Data Sheet Registers DescriptionEEPROM Content Description Reserved Offset 0E H Description Mapped priority of tag value (VLAN) Offset ADM6996L/LX Data Sheet Reset Value 040F H Reset Value 5500 H Rev. 1.13, 2005-11-22 ...
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... Source (6 bytes) Packet length (2 bytes) Byte 6~11 Byte 12~13 Offset 10 H Description Discard mode Drop scheme for Queue n Aging Status 0 E, Enable Disable B 32 ADM6996L/LX Data Sheet Registers DescriptionEEPROM Content Data (46-1500 CRC (4 bytes) bytes) Byte 14~ Reset Value Rev. 1.13, 2005-11-22 0040 H ...
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... E, Enable CRC check Disable CRC check B Reserved Broadcast Storm Filter 0 D, Disable Enable B Broadcast Storm Threshold See below Table 5 and Table 6 for details on the Broadcast Storm Threshold 01 10 10% 20 10% 0. 25% Offset ADM6996L/LX Data Sheet 50% Reset Value FF00 H Rev. 1.13, 2005-11-22 ...
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... MAC ID on this Switch. One is original Card and another one is CPU. This will make Switch learning table trouble. ADM6996L/LX provide MAC Clone function that allow two same MAC address with different VLAN ID0 on learning table. This will solve Lock registration Card’s ID issue. AT8989P serial chip will put these two same MAC addresses with different VLAN ID0 at different learning table entry ...
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... Traffic to CPU is Tag packet with VID=1. CPU can check VID to distinguish LAN traffic or WAN traffic. • WAN to CPU Traffic. ADM6996L/LX WAN traffic to CPU only. Traffic to CPU is Tag packet with VID=2. CPU can check VID to distinguish LAN traffic or WAN traffic. • CPU to LAN Packet. ...
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... LM, Lock first MAC source address B Reserved Port0 MAC Lock 0 D, Disable B 1 LM, Lock first MAC source address B Offset 13 H Description Reserved Port 5 VLAN Mapping Port 4 VLAN Mapping Port 3 VLAN Mapping Reserved 36 ADM6996L/LX Data Sheet Reset Value FFFF H Rev. 1.13, 2005-11-22 ...
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... Port 1 VLAN Mapping Reserved Port 0 VLAN Mapping bit 11. Select the VLAN group ports and set the corresponding bits Offset 23 H Description Reserved Offset 24 H Description Reserved Offset ADM6996L/LX Data Sheet Reset Value 0000 H Reset Value 0000 H Reset Value 0000 H Rev. 1.13, 2005-11-22 ...
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... Field Bits Type Res 15:0 rw Configuration Register 4 ConfigReg_4 Configuration Register 4 Data Sheet Registers DescriptionEEPROM Content Description Reserved Offset 26 H Description Reserved Offset 27 H Description Reserved Offset ADM6996L/LX Data Sheet Reset Value 0000 H Reset Value 0000 H Reset Value 0000 H Rev. 1.13, 2005-11-22 ...
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... Reserved Port1 PVID bit 11~4. 0003 PVID 1, These 8 bits combine with the register in the hex values H bit’s [13~10] as the full 12 bits of the VID. Offset 2A H Description Reserved 39 ADM6996L/LX Data Sheet Reset Value 0000 0000 H Reset Value 0000 H Rev. 1.13, 2005-11-22 ...
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... VID. Offset 2C H Description Control Reserved MAC Control reserved MAC (0180C2000000 Discard Forward B Control Reserved MAC Control reserved MAC (0180C2000001 Discard Forward B 40 ADM6996L/LX Data Sheet Reset Value 0000 H Reset Value D000 H Rev. 1.13, 2005-11-22 ...
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... CR3 12 rw Res 10 7:0 rw Note: Bit[10:8]: VLAN Tag shift register. ADM6996L/LX will select 4 bit form total 12 bit VID as VLAN group reference. Bit[15:12]: IEEE 802.3 reserved DA forward or drop police. Reserved Register 8 ResReg_8 Reserved Register 8 Field Bits Type Res 15:0 rw Reserved Register 9 ResReg_9 ...
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... H Description PHY Restart 0000 PHY Restart, Writing this Hex value to this register restarts the H internal PHYs. Offset 30 H Description Reserved Port 4 LED Mode 0 D, LinkAct/DupCol/Speed LinkAct/Speed B Reserved Reserved 42 ADM6996L/LX Data Sheet Reset Value 0000 H Reset Value 0987 H Rev. 1.13, 2005-11-22 ...
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... Port 1 Threshold Control Meter Reference table in note below. Receive Packet Length Count Counted on the Source Port 0. 0 R0, The switch will add length to the P2 counter D Port 0 Threshold Control Meter Reference table in note below. 43 ADM6996L/LX Data Sheet Reset Value 0000 H Rev. 1.13, 2005-11-22 ...
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... Counted on the Source Port 4. 0 Count4, The switch will add length to the P4 counter D Port 4 Threshold Control Meter Reference table in note below. 011 100 101 2M 5M 10M Offset ADM6996L/LX Data Sheet 110 111 20M 50M Reset Value 0000 H 110 111 20M 50M Reset Value 0000 H ...
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... D, Disable Enable B Port 3 Bandwidth Control Enable 0 D, Disable Enable B Reserved Port 2 Bandwidth Control Enable 0 D, Disable Enable B Reserved Port 1 Bandwidth Control Enable 0 D, Disable Enable B Reserved Port 0 Bandwidth Control Enable 0 D, Disable Enable B 45 ADM6996L/LX Data Sheet Rev. 1.13, 2005-11-22 ...
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... SW can read the register, with write mask the register can be cleared (1 clears) SW can read the register SW can read the register SW can read the register, with write mask the register can be cleared 46 ADM6996L/LX Data Sheet Page Number ...
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... HW (1 pdi clock cycle) Register is read and writable by SW. Description Offset 00 H Description Chip Identifier Register 0000 7101 ID, Chip Identifier H Version No 0000 Ver, Version No. H Offset ADM6996L/LX Data Sheet Reset Value 0000 0000 H Reset Value 0000 0000 H Rev. 1.13, 2005-11-22 ...
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... FC2, 802.3X on for full duplex or back pressure on for half duplex. B Port 2 Duplex Status 0 H, Half Duplex Full Duplex B Port 2 Speed Status 0 10, 10Mbps B 1 100, 100Mbps B Port 2 Linkup Status Port 2 Linkup Status: 0 NE, Link is not established Link is established. B Reserved 48 ADM6996L/LX Data Sheet Rev. 1.13, 2005-11-22 ...
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... H Description Reserved Port 5 Flow Control Enable 0 D, Flow Control Disable B 1 FC5, 802.3X on for full duplex or back pressure on for half duplex. B Port 5 Duplex Status 0 H, Half Duplex Full Duplex B 49 ADM6996L/LX Data Sheet Reset Value 0000 0000 H Rev. 1.13, 2005-11-22 ...
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... Port 3 Cable Broken Length Reserved Port 2 Cable Broken Port 2 Cable Broken Length Reserved Port 1 Cable Broken Port 1 Cable Broken Length Reserved Port 0 Cable Broken Port 0 Cable Broken Length Offset ADM6996L/LX Data Sheet Reset Value 0000 0000 H Reset Value 0000 0000 H Rev. 1.13, 2005-11-22 ...
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... Overflow of Port 1 Receive Packet Count Reserved Overflow of Port 0 Receive Packet Count Offset 3B H Description Reserved Overflow of Port 5 Transmit Packet Byte Count Overflow of Port 4 Transmit Packet Byte Count Overflow of Port 3 Transmit Packet Byte Count 51 ADM6996L/LX Data Sheet Reset Value 0000 0000 H Rev. 1.13, 2005-11-22 ...
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... Overflow of Port 3 Error Count Reserved Overflow of Port 2 Error Count Reserved Overflow of Port 1 Error Count Reserved Overflow of Port 0 Error Count Overflow of Port 5 Collision Count Overflow of Port 4Collision Count Overflow of Port 3Collision Count Reserved 52 ADM6996L/LX Data Sheet Reset Value 0000 0000 H Rev. 1.13, 2005-11-22 ...
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... Tag Control Information TCI Byte 12~13 Byte14~15 Note: ADM6996L/LX will check packet byte 12 &13. If byte[12:13]=8100h then this packet is a VLAN packet Byte 14~15: Tag Control Information TCI Bit[15:13]: User Priority 7~0 Bit 12: Canonical Format Indicator (CFI) Bit[11~0]: VLAN ID. The ADM6996L/LX will use bit[3:0] as VLAN group. ...
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... CPU with at least 100ms low. Point1 is Reset rising edge. CPU must prepare proper value on EECS(0), EESK, EDI, EDO(1) before this rising edge. ADM6996L/LX will read this value into chip at Point2. CPU must keep these values over point2. Point2 is 200ns after Reset rising edge. ...
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... Figure 4 ADM6996L/LX Serial Chip’s Internal Counter or EEPROM Access Timing Preamble: At least 32 continuous 1 Start bits) B Opcode bits, Only supports a read command) B Table select Counter EEPROM (1 bit Register Address: Read Target register address. (7 bits) TA: Turn Around. Register Data: 32 bit data. Counter output bit sequence is bit 31 to bit 0. ...
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... Reset_type: Reset the counter by port number or by counter index 1 = Clear dedicate port’s all counters Clear dedicate counter B Port_number or counter index: User defines clear port or counter Idle: EECK must send at least one clock pulse at idle time Data Sheet Registers DescriptionSerial Interface Timing ’ ADM6996L/LX Data Sheet Rev. 1.13, 2005-11-22 ...
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... TP Interface Transformer requirement: • TX/RX rate 1:1 • TX/RX central tap connect together to VCCA2 Note: Users can change the TX/RX pin for easy layout but do not change polarity. The ADM6996L/LX supports auto polarity on the receiving side TXP TXN ADM6996L RXP RXN ...
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... Data Sheet +3.3V 127 127 83 83 Symbol Values Min. Typ. V -0.3 CC Vcca2 Vccpll Vccik V -0.3 IN Vout -0.3 TSTG -55 PD ESD 58 ADM6996L/LX Electrical Specification +3. 3.3V Fiber Transceiver 1 GND_RX 2 RD VCC_RX VCC(3.3) 6 VCC_TX VCC(3.3) 7 TD- 8 TD+ 9 GND_TX +3.3V 127 182 182 SD 83 Unit Note / Test Condition Max ...
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... 1 Symbol Values Min. Typ 0.7 * Vcc 0.7 * Vcc OH R 100 I 59 ADM6996L/LX Data Sheet Electrical Specification Unit Note / Test Condition Max. 3.465 V 1.9 V 1.9 V 1.9 V Vcc V W 115 C Unit Note / Test Condition Max. 0.3 * Vcc V CMOS V CMOS 0.4 V CMOS V ...
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... Conditions Min. 100 100 10us tESKL tESKL tESKH tESKH Symbol Values Min. Typ. tESK 5120 tESKL 2550 tESKH 2550 60 ADM6996L/LX Electrical Specification 100ms tRST tRST Typical Max 20us 30us tESK tESK tERDS tERDH Unit Note / Test Condition Max. ns 2570 ns 2570 ns Rev ...
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... Symbol Values Min. Typ. t 400 CK t 180 CKL t 180 CKH t 10 RXS t 10 RXH 61 ADM6996L/LX Electrical Specification Unit Note / Test Condition Max 20us 30us tERDS tERDH Unit Note / Test Condition Max. ns 220 ns 220 Rev. 1.13, 2005-11-22 Data Sheet ...
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... Symbol Values Min. Typ. tCK 400 tCKL 180 tCKH 1 80 tTXOD 0 100ns tCK tCK tCKL tCKL tCKH tCKH tRXS tRXH 62 ADM6996L/LX Data Sheet Electrical Specification 1500ns 2000ns 2500ns Unit Note / Test Condition Max 220 200ns Rev. 1.13, 2005-11-22 ...
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... Symbol Values Min. Typ. tCK 40 tCKL 1 8 tCKH 18 tTXOD 0 63 ADM6996L/LX Data Sheet Electrical Specification Unit Note / Test Condition Max 150ns 200ns 250ns Unit Note / Test Condition Max Rev. 1.13, 2005-11-22 ...
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... Symbol Values Min. Typ. tCK 100 tCKL 40 tCKH 40 tTXS 10 tTXH 10 250ns tCK tCK tCKH tCKH 64 ADM6996L/LX Electrical Specification 500ns tCKL tCKL Unit Note / Test Condition Max 500ns tCKL tCKL Rev. 1.13, 2005-11-22 Data Sheet ...
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... Parameter GPSI_TXCLK Period GPSI_TXCLK Low Period GPSI_ T XCLK High Period GPSI_ T XCLK Rising to GPSI_TXEN/GPSI_TXD Output Delay Data Sheet Symbol Values Min. Typ. tCK 100 tCKL 40 tCKH 40 tOD 50 65 ADM6996L/LX Data Sheet Electrical Specification Unit Note / Test Condition Max Rev. 1.13, 2005-11-22 ...
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... Packaging This chapter describes the ADM6996L/LX’s packaging. 6.1 128 Pin PQFP Outside Dimension ADM6996L/LX packaging Figure 16 128-pin LQFP Chip Package Data Sheet 17.2 +/- 0.2 mm 14.0 +/- 0.1 mm 12 ADM6996L/LX Data Sheet Packaging Rev. 1.13, 2005-11-22 ...
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... TerminologyTerminology A B Data Sheet 67 ADM6996L/LX Data Sheet Rev. 1.13, 2005-11-22 ...
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Published by Infineon Technologies AG ...
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... Data Sheet 69 ADM6996L/LX Data Sheet Rev. 1.13, 2005-11-22 ...