NLXT300ZPE.F4 Intel, NLXT300ZPE.F4 Datasheet - Page 12

• Manufacturer Part Number: NLXT300ZPE.F4
• Manufacturer: Intel

Specifications of NLXT300ZPE.F4

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

LXT300Z/LXT301Z — Advanced T1/E1 Short-Haul Transceivers
2.3.2
2.4
2.4.1
2.4.2
12
Line Code
The LXT300Z and LXT301Z transmit data as a 50% AMI line code as shown in
consumption is reduced by activating the AMI line driver only to transmit a mark. The output
driver is disabled during transmission of a space.
Operating Modes
The LXT300Z and LXT301Z transceivers can be controlled through hard-wired pins (Hardware
mode). Both transceivers can also be commanded to operate in one of several diagnostic modes.
LXT300Z Only: The LXT300Z can be controlled by a microprocessor through a serial interface
(Host mode). The mode of operation is set by the MODE pin logic level.
Host Mode Operation (LXT300Z Only)
To allow a host microprocessor to access and control the LXT300Z through the serial interface,
MODE is set to 1. The serial interface (SDI/SDO) uses a 16-bit word consisting of an 8-bit
Command/Address byte and an 8-bit Data byte.
and relative timing.
The Host mode provides a latched Interrupt output (INT) which is triggered by a change in the
Loss of Signal (LOS) and/or Driver Performance Monitor (DPM) bits. The Interrupt is cleared
when the interrupt condition no longer exists, and the host processor enables the respective bit in
the serial input data byte. Host mode also allows control of the serial data and receive data output
timing. The Clock Edge (CLKE) signal determines when these outputs are valid, relative to the
Serial Clock (SCLK) or RCLK as listed in
The LXT300Z serial port is addressed by setting bit A4 in the Address/Command byte,
corresponding to address 16. The LXT300Z contains only a single output data register so no
complex chip addressing scheme is required. The register is accessed by causing the Chip Select
(CS) input to transition from High to Low. Bit 1 of the serial Address/Command byte provides
Read/Write control when the chip is accessed. A logic 1 indicates a read operation, and a logic 0
indicates a write operation.
data I/O timing characteristics are shown in the Test Specifications section.
Hardware Mode Operation (LXT300Z and LXT301Z)
In Hardware mode the transceiver is accessed and controlled through individual pins. With the
exception of the INT and CLKE functions, Hardware mode provides all the functions provided in
the Host mode. In the Hardware mode RPOS and RNEG outputs are valid on the rising edge of
RCLK. The LXT301Z operates in Hardware mode at all times.
LXT300Z Only: To operate in Hardware mode, MODE must be set Low. Equalizer Control signals
(EC1 through EC3) are input on the Interrupt, Serial Data In and Serial Data Out pins respectively.
Diagnostic control for Remote Loopback (RLOOP), Local Loopback (LLOOP), and Transmit All
Ones (TAOS) modes is provided through the individual pins used to control serial interface timing
in the Host mode.
Table 4
lists serial data output bit combinations for each status. Serial
Table
Figure 5
3.
shows the serial interface data structure
Figure
Datasheet
4. Power