TXC-03303-ARPQ Transwitch Corporation, TXC-03303-ARPQ Datasheet - Page 6

• Manufacturer Part Number: TXC-03303-ARPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03303-ARPQ

• Lead Free Status / RoHS Status: Compliant

M13E
TXC-03303
The M13E synchronizes and extracts the 28 DS1 channels from the seven DS2 channels. Each of the DS2
channels is monitored for out of frame. The M13E may generate AIS in each of the DS1 signal tributaries cor-
responding to the DS2 channel(s) that lost frame, depending on the DS1 AIS alarm insertion control bits. DS2
to DS1 destuffing is based on the states of the three C-bits in each DS2 subframe. If two or three of the C-bits
in one of the DS2 subframes are ones, the stuff bit for that subframe is discarded. In the M13 mode, the DS2
C-bits or stuffing bits are used for DS1 remote loopback requests. The M13E provides control bits in the mem-
ory map for selecting the remote loopback detection mechanism. The destuffing operation is still active during
loopback request and operation. In addition to DS2 synchronization, destuffing, and remote loopback detec-
tion, the M13E also extracts the seven DS2 X-bits.
An option is provided that allows the received or transmitted DS1 channels to be monitored for loss of signal.
Receive data for each of the DS1 channels (DRn) is clocked out of the M13E on positive transitions of the
associated clock signal (CRn). In addition, the M13E provides a stable DS1 clock signal for the data signals
received during AIS periods.
In the transmit direction, DS1 transmit data (DTn) is clocked into the M13E on positive transitions of the clock
input (CTn) for each of the 28 DS1 channels. A DS1 Input Block, which consists of a FIFO and supporting
logic, is provided for each DS1 channel. Under software control, the M13E can invert the transmit data signals,
or the clock signals, for all 28 DS1 channels. The data inversion feature provides compatibility with certain T1
line interface devices, while the clock inversion feature allows back-to-back M13 operation.
The DS1 Input Block is also used to insert one of three idle patterns from a common generator into a DS1 bit
stream, under software control. The selection of the idle pattern is common to all 28 DS1 channels. The idle
patterns are: a QRS, an Extended Super Frame DS1 (ESF) format with all ones in channels 1 through 28, and
an AIS format (all ones).
Each DS1 signal is multiplexed into the respective DS2 frame, with the stuff bits inserted based on the fill level
of an internal FIFO. When the fill of the FIFO drops below half full, a stuff bit is inserted into the DS1 bit stream
in the DS2 signal. The DS2 signal is formed by combining four DS1 signals. In each frame there are 287 data
bit positions and one stuff bit per DS1 channel (for a DS1 total of 1152 bits) and 24 overhead bits, for a frame
total of 1176 bits. The overhead bits are used for framing, X-bit channel and stuff control.
The DS3 signal is partitioned into M-frames of 4760 bits each. The M-frames are divided into seven
M-subframes having 680 bits each. Each M-subframe is further divided into eight blocks of 85 bits each. Each
block uses 84 bits for payload and one bit for frame overhead. There are 56 overhead bits in each M-frame:
the M-frame alignment uses three bits, the M-subframe alignment (F-bits) uses 28 bits, 21 bits are defined as
C-bits, two bits are assigned for parity, and two bits are assigned for the X-bit channel.
The DS3 frame is constructed and timed according to the operating mode, i.e., C-bit parity mode or M13 mode.
In the C-bit parity mode, all seven of the DS2 stuff bits are fixed as stuff, resulting in 7 pseudo DS2 frames of
671 bits per DS2 frame in each DS3 frame, for a DS2 rate of 6.3062723 Mbit/s. Since stuffing always occurs,
the 21 C-bits are assigned for other functions, as shown in Figure 2. A C-bit interface is provided for transmit-
ting 13 or 14 C-bits (C2, C3-depending on the state of bit 7 of register 19H (C3CLKI), C4, C5, C6, C13, C14,
C15, C16, C17, C18, C19, C20, C21). The external transmit C-bit interface consists of a serial data input
(CDT), an output clock (CCKT), a data link indicator pulse (CDCCT), and an output framing pulse (CFMT). The
data link indicator pulse identifies the location of the three data link bits, C13, C14, and C15. In addition, a con-
trol bit is provided in the memory map which enables the M13E to generate an extra clock cycle during the C3
bit time. A receive C-bit interface is provided for extraction of 14 C-bits (C2, C3, C4, C5, C6, C13, C14, C15,
C16, C17, C18, C19, C20, C21). The receive C-bit interface consists of a serial data output (CDR), an output
clock (CCKR), a data link indicator pulse (CDCCR), and an output framing pulse (CFMR). The data link indica-
tor pulse identifies the location of the three data link C-bits, C13, C14, and C15.
TXC-03303-MB
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Ed. 4, August 1998