82P2821BH IDT, Integrated Device Technology Inc, 82P2821BH Datasheet - Page 42

• Manufacturer Part Number: 82P2821BH
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2821BH

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.4
transmitter. Each Jitter Attenuator can be enabled or disabled, as deter-
mined by the RJA_EN/TJA_EN bit (b3, RJA/TJA,...) respectively.
Figure-23.
data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the RJA_DP[1:0]/
TJA_DP[1:0] bits (b2~1, RJA/TJA,...). Accordingly, the typical delay
produced by the Jitter Attenuator is 16 bits, 32 bits or 64 bits. The 128-
bit FIFO is used when large jitter tolerance is expected, while the 32-bit
FIFO is used in delay sensitive applications.
Functional Description
IDT82P2821
Jittered Data
Jittered Clock
Two Jitter Attenuators are provided for each channel of receiver and
Each Jitter Attenuator consists of a FIFO and a DPLL, as shown in
The FIFO is used as a pool to buffer the jittered input data, then the
JITTER ATTENUATOR (RJA & TJA)
Figure-23 Jitter Attenuator
clock
write
32/64/128
DPLL
FIFO
clock
read
De-jittered Data
De-jittered Clock
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
42
stored in the FIFO. The DPLL can only attenuate the incoming jitter
whose frequency is above Corner Frequency (CF) by 20 dB per decade
falling off. The jitter whose frequency is lower than the CF passes
through the DPLL without any attenuation. In T1/J1 applications, the CF
of the DPLL is 5 Hz or 1.26 Hz. In E1 applications, the CF of the DPLL is
6.77 Hz or 0.87 Hz. The CF is selected by the RJA_BW/TJA_BW bit (b0,
RJA/TJA,...). The lower the CF is, the longer time is needed to achieve
synchronization.
will overflow. If the incoming data moves slower than the outgoing data,
the FIFO will underflow. The overflow and underflow are both captured
by the RJA_IS/TJA_IS bit (b5/6, INTS0,...). The occurrence of overflow
or underflow will be reported by the INT pin if enabled by the RJA_IM/
TJA_IM bit (b5/6, INTM0,...).
by setting the RJA_LIMT/TJA_LIMT bit (b4, RJA/TJA,...). When the JA-
Limit function is enabled, the speed of the outgoing data will be adjusted
automatically if the FIFO is 2-bit close to its full or emptiness. Though
the JA-Limit function can reduce the possibility of FIFO overflow and
underflow, the quality of jitter attenuation is deteriorated.
G.736-739, G.823, G.824, ETSI 300011, ETSI TBR12/13, AT&T
TR62411, TR43802, TR-TSY 009, TR-TSY 253 and TR-TRY 499. Refer
to Section 8.12 Jitter Attenuation Characteristics for the jitter perfor-
mance.
The DPLL is used to generate a de-jittered clock to clock out the data
If the incoming data moves faster than the outgoing data, the FIFO
To avoid overflow or underflow, the JA-Limit function can be enabled
The performance of the Jitter Attenuator meets ITUT I.431, G.703,
February 6, 2009