CY7C924ADX-AI Cypress Semiconductor Corp, CY7C924ADX-AI Datasheet - Page 19

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CY7C924ADX-AI

Manufacturer Part Number
CY7C924ADX-AI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C924ADX-AI

Number Of Transceivers
1
Data Rate
622Mbps
Operating Supply Voltage (typ)
5V
Supply Current (max)
250mA
Screening Level
Industrial
Pin Count
100
Mounting
Surface Mount
Package Type
TQFP
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C924ADX-AI
Manufacturer:
CYPRESS
Quantity:
240
Part Number:
CY7C924ADX-AI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Company:
Part Number:
CY7C924ADX-AI
Quantity:
588
Document #: 38-02008 Rev. *E
Table 5. Speed Select and Range Select Settings, all modes
External Control of Data Flow
The Transmit Control State Machine supports three different
types of external control:.
These control signal inputs are only interpreted when the
Transmit FIFO is enabled. They affect the transmission of data
by bringing external signals to the state machine without
sending the signals through the Transmit FIFO.
TXSTOP* stops transmission of the next packet or cell of data
in the Transmit FIFO. When asserted (LOW) the Transmit
Control State Machine continues to read and process
characters in the Transmit FIFO until a location is read with the
TXSOC bit set. Once a TXSOC is detected, the state machine
sends out C5.0 fill characters until TXSTOP* is deasserted
(HIGH) for one or more character times. When TXSTOP* is
sampled deasserted it allows the next character with TXSOC
set to be read from the Transmit FIFO and passed to the
Encoder.
• TXSTOP*
• TXHALT*
• TXINT
FIFOBYP*
HIGH
LOW
BYTE8/10*
HIGH
HIGH
LOW
LOW
ENCBYP*
HIGH
HIGH
LOW
LOW
X
X
SPDSEL
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
RANGESEL
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
When TXSTOP* controls the flow of data, it is asserted (LOW)
most of the time. To allow a cell or frame to pass, it only needs
to be deasserted (HIGH) for one TXCLK cycle (assuming the
transmit controller is at a cell boundary). Once the first
character of the cell is transmitted the remainder of that cell is
also processed. This allows the host system to control the
transmission of data across the interface on a cell-by-cell or
packet-by-packet basis.
TXHALT* (TXDATA[9]) is an immediate form of TXSTOP*.
Instead of continuing to transmit data until a TXSOC is found,
asserting TXHALT* stops character processing at the next
FIFO character location. No additional data is read from the
Transmit FIFO until TXHALT* is deasserted (HIGH).
Note. If the Encoder is bypassed, TXDATA[9] is a data input
and not TXHALT*. Since in this mode the interface does not
interpret the TXSOC bit, the TXSTOP* signal assumes the
same functionality as TXHALT*.
TXINT is used to send one of two interrupt characters from the
local transmitter to a remote receiver. While it also bypasses
the Transmit FIFO, it does not directly stop data transmission.
The Transmit Control State Machine responds to transitions on
the TXINT input. When TXINT transitions from 0→1, a C0.0
16.67 -33.33
16.67 -33.33
16.67 -33.33
16.67 -33.33
Frequency
8.33-16.67
8.33-16.67
8.33-16.67
8.33-16.67
REFCLK
(MHz)
10-20
20-40
10-20
20-40
10-20
20-40
10-20
20-40
10-20
20-40
10-20
20-40
10-20
20-40
10-20
20-40
Serial Data Rate
100-200
100-200
100-200
100-200
100-200
100-200
100-200
100-200
100-200
100-200
100-200
100-200
100-200
100-200
100-200
50-100
50-100
50-100
50-100
50-100
50-100
50-100
50-100
50-100
(MBd)
CY7C924ADX
Page 19 of 58
Multiplier
Factor
x2.5
x2.5
x10
x10
x12
x10
x10
x12
x5
x5
x5
x5
x6
x5
x5
x6
x3
x6
x5
x5
x5
x5
x6
x6
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