CY7C924ADX-AI Cypress Semiconductor Corp, CY7C924ADX-AI Datasheet - Page 48

• Manufacturer Part Number: CY7C924ADX-AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C924ADX-AI

• Number Of Transceivers: 1
• Data Rate: 622Mbps
• Operating Supply Voltage (typ): 5V
• Supply Current (max): 250mA
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02008 Rev. *E
Serial Address Register Access
The Serial Address Register in the CY7B924ADX is accessed
through the RXDATA bus. This Serial Address Register can
only be accessed in UTOPIA mode (EXTFIFO = L). This
register can be both written and read, and is accessed by
asserting RXRST* to address the register in the device instead
of the normal Receive FIFO data. Within this alternate address
space, the RXRVS signal is an input at all times, and is used
to select between read (RXRVS is HIGH) and write (RXRVS
is LOW) operations on the Serial Address Register.
The Serial Address Register is the same size as the 8- or 10-bit
data width selected by BYTE8/10*. It can be set to match
domain or multicast addresses by the level on RXSC/D*. If
RXS/D* is LOW when the Serial Address Register is written, it
becomes the Multicast address register and declares a match
if at least one bit matches the equivalent bit in the incoming
Address character. If RXSC/D* is HIGH when the Serial
Address Register is written, it becomes the Unicast address
register and defines a match only if all of the bits match the
incoming Address character.
This register mapping is shown in
Accessing Serial Address Register
To access the Serial Address Register in the CY7B924ADX,
an Rx_RstMatch condition must first be generated by the
combined assertion of AM* and RXRST* and the device must
be in UTOPIA timing mode (EXTFIFO = L). RXEN* is then
used as the data strobe signal to initiate either a read or write
cycle to the RXDATA bus. If RXRVS is HIGH at the time of the
RXEN* data strobe, a register read operation takes place. If
RXRVS is LOW at the time of the RXEN* data strobe, a
register write operation takes place.
The RXSC/D* input is used in conjunction with RXDATA[9:0]
or RXDATA[7:0] to select the operational mode of the Serial
Address Register (Unicast or Multicast)
Rx_FIFO_Reset
Rx_RstMatch
(R/W input)
RXDATA
RXSC/D*
RXRST*
RXRVS
RXCLK
RXEN*
AM*
[26]
[26]
Figure 6 on page
Figure 16. Serial Address Register Access
Write Register
25.
Register write and read operations are shown in
the serial address register write and read operations are both
performed without deasserting RXRST* for at more than
seven cycles, then RXRST* will still not extend to the
requirement for a reset and the Receive FIFO will not be reset.
FIFO Reset, Serial Address Register Access and Continuous
Selection
When configured for continuous selection (AM* asserted with
TXEN* always enabled, or AM* asserted with RXEN* always
enabled), it is not possible to reset the Transmit and Receive
FIFOs. It is also not possible to write to the Serial Address
Register without deselecting the Receive FIFO interface.
X3.230 Codes and Notation Conventions
Information to be transmitted over a serial link is encoded eight
bits at a time into a 10-bit Transmission Character and then
sent serially, bit by bit. Information received over a serial link
is collected ten bits at a time, and those Transmission
Characters that are used for data (Data Characters) are
decoded into the correct eight-bit codes. The 10-bit Trans-
mission Code supports all 256 8-bit combinations. Some of the
remaining Transmission Characters (Special Characters) are
used for functions other than data transmission.
The primary rationale for use of a Transmission Code is to
improve the transmission characteristics of a serial link. The
encoding defined by the Transmission Code ensures that suffi-
cient transitions are present in the serial bit stream to make
clock recovery possible at the Receiver. Such encoding also
greatly increases the likelihood of detecting any single or
multiple bit errors that may occur during transmission and
reception of information. In addition, some Special Characters
of the Transmission Code selected by Fibre Channel Standard
consist of a distinct and easily recognizable bit pattern (the
Special Character Comma) that assists a Receiver in
achieving word alignment on the incoming bit stream.
Read Register
CY7C924ADX
Page 48 of 58
Figure
16. If
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