LAN91C111-NU Standard Microsystems (SMSC), LAN91C111-NU Datasheet
LAN91C111-NU
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LAN91C111-NU Summary of contents
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... Supports Multiple Embedded Processor Host Interfaces — ARM — SH — Power PC — Coldfire — 680X0, 683XX — MIPS R3000 SMSC LAN91C111 REV C LAN91C111 10/100 Non-PCI Ethernet Single Chip MAC + PHY 3.3V MII (Media Independent Interface) MAC-PHY Interface Running at Nibble Rate MII Management Serial Interface 128-Pin QFP lead-free RoHS compliant package 128-Pin TQFP 1 ...
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... LAN91C111-NS, LAN91C111i-NS (INDUSTRIAL TEMPERATURE) FOR 128-PIN QFP LEAD-FREE ROHS COMPLIANT PACKAGES LAN91C111-NU (1.0MM HEIGHT); LAN91C111i-NU (INDUSTRIAL TEMPERATURE) FOR 128-PIN TQFP LEAD-FREE ROHS COMPLIANT PACKAGES 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2009 SMSC or its subsidiaries. All rights reserved. ...
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... Receive Polarity Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.7.15 Full Duplex Mode 7.7.16 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.7.17 PHY Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.7.18 PHY Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Chapter 8 MAC Data Structures and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1 Frame Format In Buffer Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.2 Receive Frame Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.3 I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 SMSC LAN91C111 REV C 3 DATASHEET Revision 1.91 (06-01-09) ...
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... Chapter 13 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13.1 Maximum Guaranteed Ratings 105 13.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13.3 Twisted Pair Characteristics, Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 13.4 Twisted Pair Characteristics, Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Chapter 14 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 4 DATASHEET Datasheet SMSC LAN91C111 REV C ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 15 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Chapter 16 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SMSC LAN91C111 REV C 5 DATASHEET Revision 1.91 (06-01-09) ...
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... List of Figures Figure 2.1 Pin Configuration - LAN91C111-FEAST 128 PIN TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2.2 Pin Configuration - LAN91C111-FEAST 128 PIN QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3.1 Basic Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 3.3 LAN91C111 Physical Layer to Internal MAC Block Diagram Figure 7.1 MI Serial Port Frame Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 7.2 MII Frame Format & ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet List of Tables Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP and 1.0mm TQFP package Table 7.1 4B/5B Symbol Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 7.2 Transmit Level Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 8.1 Internal I/O Space Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 9.1 MII Serial Frame Structure Table 9 ...
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... Internal output wave shaping circuitry and on-chip filters eliminate the need for external filters normally required in 100Base-TX and 10Base-T applications. The LAN91C111 can automatically configure itself for 100 or 10 Mbps and Full or Half Duplex operation with the on-chip Auto-Negotiation algorithm. The LAN91C111 is ideal for media interfaces for embedded application desiring Ethernet connectivity as well as 100Base-TX/10Base-T adapter cards, motherboards, repeaters, switching hubs ...
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... LBK 21 nLEDA 22 nLEDB 23 GND 24 MDI 25 MDO 26 MCLK 27 nCNTRL 28 INTR0 29 RESET 30 nRD 31 nWR 32 Figure 2.1 Pin Configuration - LAN91C111-FEAST 128 PIN TQFP SMSC LAN91C111 REV C Pin Configuration LAN91C111- TM FEAST 128 PIN TQFP 9 DATASHEET 96 nBE2 95 nBE1 94 nBE0 93 GND 92 A15 91 A14 90 A13 89 A12 88 A11 ...
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... INTR0 31 RESET 32 nRD 33 nWR 34 VDD 35 nDATACS 36 nCYCLE 37 W/nR 38 Figure 2.2 Pin Configuration - LAN91C111-FEAST 128 PIN QFP Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY Pin Configuration LAN91C111- TM FEAST 128 PIN QFP 10 DATASHEET Datasheet 102 D6 101 D7 100 VDD 99 nBE3 ...
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... Chapter 3 Block Diagrams The diagram shown in Figure 3.1, "Basic Functional Block Diagram", describes the device basic functional blocks. The SMSC LAN91C111 is a single chip solution for embedded designs with minimal Host and external supporting devices required to implement 10/100 Ethernet connectivity solutions. ...
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... Generic Embedded. The Host interface bit wide address / data bus with extensions for 32, 16 and 8 bit embedded RISC and ARM processors. The figure shown next page describes the SMSC LAN91C111 functional blocks required to integrate a 10/100 Ethernet Physical layer framer to the internal MAC. ...
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... TXEN100 TX25 CRS100 COL100 RXD[3:0] RX_ER RX_DV RX25 MII MDI SERIAL MCLK Manage MDO -ment MII Power PHY AUTONEG On CONTROLS LOGIC Reset Figure 3.3 LAN91C111 Physical Layer to Internal MAC Block Diagram SMSC LAN91C111 REV C LS[2-0]A LED Control 13 DATASHEET Multiplexer LEDA nPLED[0- ...
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... Chapter 4 Signal Descriptions Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP and 1.0mm TQFP package) FUNCTION System Address Bus System Data Bus System Control Bus Serial EEPROM LEDs PHY Crystal Oscillator Power Ground Physical Interface (MII) MISC TOTAL Revision 1.91 (06-01-09) ...
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... SMSC LAN91C111 REV C BUFFER SYMBOL DESCRIPTION TYPE A4-A15 I** Input. Decoded by LAN91C111 to determine access to its registers. A1-A3 I** Input. Used by LAN91C111 for internal register selection. AEN I** Input. Used as an address qualifier. Address decoding is only enabled when AEN is low. nBE0- I** Input. Used during LAN91C111 register nBE3 ...
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... I with Input. When nDATACS is low, the Data pullup** Path can be accessed regardless of the values of AEN, A1-A15 and the content of the BANK SELECT Register. nDATACS provides an interface for bursting to and from the LAN91C111 32 bits at a time. 16 DATASHEET Datasheet SMSC LAN91C111 REV C ...
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... EEPROM configurations. ENEEP I with Input. Enables (when high or open) pullup** LAN91C111 accesses to the serial EEPROM. Must be grounded if no EEPROM is connected to the LAN91C111. XTAL1 Iclk** An external 25 MHz crystal is connected XTAL2 across these pins TTL clock is supplied instead, it should be connected to XTAL1 and XTAL2 should be left open ...
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... MCLK O4 MII management clock. RX_ER I with Input. Indicates a code error detected by pulldown PHY. Used by the LAN91C111 to discard the packet being received. The error indication reported for this event is the same as a bad CRC (Receive Status Word bit 13). nCSOUT O4 Output. Chip Select provided for mapping of PHY functions into LAN91C111 decoded space ...
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... Datasheet Chapter 6 Signal Description Parameters This section provides a detailed description of each SMSC LAN91C111 signal. The signals are arranged in functional groups according to their associated function. The ‘n’ symbol at the beginning of a signal name indicates that active low signal. When ‘n’ is not present before the signal name, it indicates an active high signal. The term “ ...
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... It also determines the value of the transmit and receive interrupts as a function of the queues. The page size is 2048 bytes, with a maximum memory size of 8kbytes. MIR values are interpreted in 2048 byte units. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 20 DATASHEET Datasheet SMSC LAN91C111 REV C ...
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... The data path connection between the MAC and the internal PHY is provided by the internal MII. The LAN91C111 also supports the EXT_PHY mode for the use of an external PHY, such as HPNA. This mode isolates the internal PHY to allow interface with an external PHY through the MII pins ...
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... Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY Figure 7.1. The Ml serial port is idle when at Table 9.1 Figure 7.1 are start bits and need to be written for the serial port 22 DATASHEET Datasheet and timing diagram of a frame is SMSC LAN91C111 REV C ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet Figure 7.1 MI Serial Port Frame Timing Diagram SMSC LAN91C111 REV C 23 DATASHEET Revision 1.91 (06-01-09) ...
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... MII Packet Data Communication with External PHY The MIl is a nibble wide packet data interface defined in IEEE 802.3. The LAN91C111 meets all the MIl requirements outlined in IEEE 802.3 and shown in TX_EN = 0 IDLE PREAMBLE PRMBLE 62 BT FIRST BIT LSB FIRST NIBBLE ...
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... Internal Physical Layer The LAN91C111 integrates the IEEE 802.3 physical layer (PHY) internally. The EXT PHY bit in the Configuration Register the default configuration to set the internal PHY enabled. The internal PHY address is 00000, the driver must use this address to talk to the internal PHY. The internal PHY is placed in isolation mode at power up and reset ...
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... WITH NO MID BIT TRANSITION Figure 7.3 TX/10BT Frame Format 26 DATASHEET Datasheet INTERFRAME GAP LN LLC DATA FCS LN FCS ESD LLC DATA IDLE BEFORE / AFTER 4B5B ENCODING, SCRAMBLING, AND MLT3 CODING LN LLC DATA FCS SOI IDLE BEFORE / AFTER MANCHESTER ENCODING SMSC LAN91C111 REV C ...
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... The mapping of the 5B nibbles to the 4B code words is specified in IEEE 802.3. The 4B5B decoder on the LAN91C111 takes the 5B code words from the descrambler, converts them into 4B nibbles per Table 2, and sends the 4B nibbles to the controller interface. The 4B5B decoder also strips off the SSD delimiter (a ...
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... In Manchester coded data, the first half of the data bit contains the complement of the data, and the second half of the data bit contains the true data. The Manchester decoder in the LAN91C111 converts the Manchester encoded data stream from the TP receiver into NRZ data for the controller interface by decoding the data and stripping off the SOI pulse ...
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... Scrambler 100 Mbps 100BASE-TX requires scrambling to reduce the radiated emissions on the twisted pair. The LAN91C111 scrambler takes the encoded data from the 4B5B encoder, scrambles it per the IEEE 802.3 specifications, and sends it to the TP transmitter. 10 Mbps A scrambler is not used in 10Mbps mode. ...
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... Ohm unshielded twisted pair cable or 150 Ohm shielded twisted pair cable tied directly to the TP output pins without any external filters. During the idle period, no output signal is transmitted on the TP outputs (except link pulse). Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 30 DATASHEET Datasheet Figure 7.4. The SMSC LAN91C111 REV C ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet B 1.0 0.8 0.6 0.4 C 0.2 0.0 A -0.2 -0.4 -0.6 -0.8 -1 Figure 7.4 TP Output Voltage Template - 10 MBPS REFERENCE SMSC LAN91C111 REV TIME (ns) TIME (NS) INTERNAL MAU 100 110 31 DATASHEET 100 VOLTAGE (V) 0 1.0 0.4 0.55 ...
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... TIME (NS) INTERNAL MAU 111 111 111 110 100 110 90 Table 7.2 Transmit Level Adjust 32 DATASHEET Datasheet VOLTAGE (V) 0.15 0 -0.15 -1.0 -0.3 -0.7 -0.7 GAIN 1.16 1.14 1.12 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 0.88 0.86 SMSC LAN91C111 REV C ...
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... The TP transmitter can be powered down by setting the transmit powerdown bit in the PHY Ml serial port Configuration 1 register. When the transmit powerdown bit is set, the TP transmitter is powered down, the TP transmit outputs are high impedance, and the rest of the LAN91C111 operates normally. 7.7.8 Twisted Pair Receiver ...
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... CRS100 is asserted, and (6) the receiver meets the squelch requirements defined in IEEE 802.3 Clause 14. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY a. Short Bit 3.1V Slope 0 585 mV sin ( t/PW Long Bit Slope 0 t/PW) * 585 mV sin [ PW/2)/PW] 3PW/4 PW/4 34 DATASHEET Datasheet 585mV 3.1V 585mV PW SMSC LAN91C111 REV C ...
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... If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is neither /I/I/ nor /J/K/ symbols but contains at least 2 non contiguous 0's, then activity is detected but the start of packet is considered to be faulty and a False Carrier Indication (also referred to as bad SMSC LAN91C111 REV C 35 DATASHEET ...
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... The receive SOI pulse is detected by the TP receiver by sensing missing data transitions. Once the SOI pulse is detected, data reception is ended and the MAC is notified of no data/invalid data received. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 36 DATASHEET Datasheet SMSC LAN91C111 REV C ...
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... AutoNegotiation is only specified for 100BASE-TX and 10BASE-T operation. 10BASE-T Link Integrity Algorithm - 10Mbps The LAN91C111 uses the same 10BASE-T link integrity algorithm that is defined in IEEE 802.3 Clause 14. This algorithm uses normal link pulses, referred to as NLP's and transmitted during idle periods, to determine if a device has successfully established a link with a remote device (called Link Pass State) ...
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... IEEE 802.3 Clause 28. AutoNegotiation uses a burst of link pulses, called fast link pulses and referred to as FLP'S, to pass bits of signaling data back and forth between the LAN91C111 and a remote device. The transmit FLP pulses meet the templated specified in IEEE 802.3 and shown ...
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... IEEE 802.3 Clause 28. Once the negotiation process is completed, the LAN91C111 then configures itself for either 10 or 100 Mbps mode and either Full or Half Duplex modes (depending on the outcome of the negotiation process), and it switches to either the 100BASETX or 10BASE-T link integrity algorithms (depending on which mode was enabled by AutoNegotiation) ...
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... PHY Ml serial port Status Output register. The LAN91C111 will automatically correct for the reverse polarity condition provided that the autopolarity feature is not disabled. Note: The first 3 received packets must be discarded after the correction of a reverse polarity condition ...
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... PHY Powerdown The internal PHY of LAN91C111 can be powered down by setting the powerdown bit in the PHY Ml serial port Control register. In powerdown mode, the TP outputs are in high impedance state, all functions are disabled except the PHY Ml serial port, and the power consumption is reduced to a minimum. To restore PHY to normal power mode, set the PDN bit in PHY MI Register The PHY is then in isolation mode (MII_DIS bit is set) ...
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... Software driver requires to wait for 50mS after setting the RST bit to high to access the internal PHY again. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 42 DATASHEET Datasheet SMSC LAN91C111 REV C ...
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... BYTE COUNT - Divided by two, it defines the total number of words including the STATUS WORD, the BYTE COUNT WORD, the DATA AREA, the CRC, and the CONTROL BYTE. The CRC is not included if the STRIP_CRC bit is set. The maximum number of bytes in a RAM page is 2048 bytes. SMSC LAN91C111 REV C 2nd Byte STATUS WORD ...
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... CPU, including the source address. The LAN91C111 does not insert its own source address. On receive, all bytes are provided by the CSMA side. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C111 treated transparently as data both for transmit and receive operations. ...
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... The odd byte can be accessed using address (offset + 1). Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight bit registers, in that case the offset of each one is independently specified. SMSC LAN91C111 REV C HASH VALUE 5-0 000 000 010 000 ...
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... BANK7 is selected (BS0=BS1=BS2=1), and A3=0, nCSOUT is activated to facilitate implementation of external registers. Note: BANK7 does not exist in LAN91C9x devices. For backward S/W compatibility BANK7 accesses should be done if the Revision Control register indicates the device is the LAN91C111. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY Table 8 ...
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... NOCRC - Does not append CRC to transmitted frames when set. Allows software to insert the desired CRC. Defaults to zero, namely CRC inserted. PAD_EN - When set, the LAN91C111 will pad transmit frames shorter than 64 bytes with 00. For TX, CPU should write the actual BYTE COUNT before padded by the LAN91C111 to the buffer RAM, excludes the padded 00 ...
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... CPU. When TXENA is enabled with no packets in the queue and while the FORCOL bit is set, the LAN91C111 will transmit a preamble pattern the next time a carrier is seen on the line packet is queued, a preamble and SFD will be transmitted. This bit defaults low to normal operation ...
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... SOFT_RST - Software-Activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low. The LAN91C111’s configuration is not preserved except for Configuration, Base, and IA0-IA5 Registers. EEPROM is not reloaded after software reset. FILT_CAR - Filter Carrier. When set filters leading edge of carrier sense for 12 bit times (3 nibble times) ...
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... ABORT_ENB - Enables abort of receive when collision occurs. Defaults low. When set, the LAN91C111 will automatically abort a packet being received when the appropriate collision input is activated. This bit has no effect if the SWFDUP bit in the TCR is set. STRIP_CRC - When set, it strips the CRC on received frames result, both the Byte Count and the frame format do not contain the CRC ...
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... Register) is clear. DPLX – Duplex Select - This bit selects Full/Half Duplex operation. This bit is valid and selects duplex operation only when the ANEG Bit = 0, this bit overrides the DPLX bit in the PHY Register 0 (Control SMSC LAN91C111 REV C NAME TYPE REGISTER ...
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... FOR THE MAC 10_FDX 10_HDX SWFDUP Bit Bit Bit Register Register Transmit 4 4 Control (PHY) (PHY) Register (MAC DUPLEX MODE CONTROL FOR THE MAC SPEED DPLX SWFDUP Bit Bit Bit Register Register Transmit 0 0 Control (PHY) (PHY) Register (MAC SMSC LAN91C111 REV C ...
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... Half Duplex LS2A, LS1A, LS0A – LED select Signal Enable. These bits define what LED control signals are routed to the LEDA output pin on the LAN91C111 Ethernet Controller. The default is 10/100 Link detected. LS2A LS1A LS0A LED SELECT SIGNAL – LEDA 0 ...
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... TX and RX clock so that the Ethernet MAC will no longer be able to receive and transmit packets. The Host interface however, will still be active allowing the Host access to the device through Standard IO access. All LAN91C111 registers will still be accessible. However, status and control will not be allowed until the EPH Power EN bit is set AND a RESET MMU command is initiated. ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.12 Bank 1 - Base Address Register OFFSET 2 This register holds the I/O address decode option chosen for the LAN91C111 part of the EEPROM saved setup and is not usually modified during run-time. HIGH A15 A14 BYTE ...
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... This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control Register is set. This allows generic EEPROM read and write routines that do not affect the basic setup of the LAN91C111. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY ...
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... The remaining 14 bits of this register will be invalid. During this time attempted read/write operations, other than polling the EEPROM status, will NOT have any effect on the internal registers. The CPU can resume accesses to the LAN91C111 after both bits are low. A worst case RELOAD operation initiated by RESET or by software takes less than 750 μs. ...
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... Can be used following 3) to release receive packet memory in a more flexible way than 4). Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY NAME TYPE WRITE ONLY MMU COMMAND BUSY BIT REGISTER READABLE Reserved Reserved 58 DATASHEET Datasheet SYMBOL MMUCR Reserved Reserved BUSY 0 SMSC LAN91C111 REV C ...
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... PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is accessible through the TX area. Some MMU commands use the number stored in this register as the packet number parameter. This register is cleared by a RESET or a RESET MMU Command. SMSC LAN91C111 REV C NAME TYPE ...
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... REMPTY is clear. The packet is removed from the RX FIFO using MMU Commands 3) or 4). Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY NAME TYPE REGISTER READ ONLY ALLOCATED PACKET NUMBER 0 0 NAME TYPE READ ONLY RX FIFO PACKET NUMBER FIFO PACKET NUMBER DATASHEET Datasheet SYMBOL ARR SYMBOL FIFO SMSC LAN91C111 REV C ...
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... NOT EMPTY - When set indicates that the Write Data FIFO is not empty yet. The CPU can verify that the FIFO is empty before loading a new pointer value. This is a read only bit. Note: If AUTO INCR. is not set, the pointer must be loaded with a dword aligned value. SMSC LAN91C111 REV C NAME TYPE ...
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... This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C111 regardless of whether the pointer address is even, odd or dword aligned. Data goes through the write FIFO into memory, and is pre-fetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte can be accessed through the Data Low or Data High registers ...
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... CTR_ROL - Statistics counter roll over TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low and the specific reason will be reflected by the bits: SQET - SQE Error LOST CARR - Lost Carrier SMSC LAN91C111 REV C NAME TYPE INTERRUPT ACKNOWLEDGE REGISTER ...
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... FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the FIFO PORTS register. Receive Interrupt is cleared when RX FIFO is empty. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 64 DATASHEET Datasheet SMSC LAN91C111 REV C ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C111 REV C Figure 8.2 Interrupt Structure 65 DATASHEET Revision 1.91 (06-01-09) ...
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... Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY NAME TYPE READ/WRITE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE DATASHEET Datasheet SYMBOL SMSC LAN91C111 REV C ...
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... OFFSET A REVISION REGISTER HIGH BYTE 0 0 LOW CHIP BYTE 1 0 CHIP - Chip ID. Can be used by software drivers to identify the device used. REV - Revision ID. Incremented for each revision of a given device. SMSC LAN91C111 REV C NAME TYPE MANAGEMENT INTERFACE READ/WRITE Reserved Reserved Reserved MDOE 1 ...
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... RCV DISCRD is self clearing. MBO - Must be 1. 8.26 Bank 7 - External Registers OFFSET 0 THROUG H 7 EXTERNAL REGISTERS nCSOUT is driven low by the LAN91C111 when a valid access to the EXTERNAL REGISTER range occurs. HIGH BYTE LOW BYTE Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY NAME ...
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... NCSOUT AEN=0 Driven low. Transparently latched on nADS A3=0 rising edge. A4-15 matches I/O BASE BANK SELECT = 7 BANK SELECT = 4,5,6 High Otherwise High SMSC LAN91C111 REV C LAN91C111 DATA BUS Ignored on writes. Tri-stated on reads. Ignore cycle. Normal LAN91C111 cycle. 69 DATASHEET Revision 1.91 (06-01-09) ...
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... Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY R/WSC: Read/Write Self Clearing R/LH: Read/Latch high R/LL: Read/Latch low REGISTER NAME Control Status PHY ID Auto-Negotiation Advertisement Auto-Negotiation Remote End Capability Reserved Configuration 1 70 DATASHEET Datasheet SMSC LAN91C111 REV C ...
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... When ST[1:0]=01 Serial Port access cycle starts. ST0 READ Read Select 1 = Read Cycle WRITE Write Select 1 = Write Cycle PHYAD[4:0] Physical PHYSICAL ADDRESS Device Address SMSC LAN91C111 REV C REGISTER NAME Configuration 2 Status Output Table 9.1 MII Serial Frame Structure <PHY Addr.> <REG.Addr.> PHYAD[4:0] REGAD[4:0] 71 DATASHEET Mask Reserved < ...
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... D[15:0].... Data These 16 bits contain data to/from one of the eleven registers selected by register address bits REGAD[4:0]. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 72 DATASHEET Datasheet R/W W R/W Any SMSC LAN91C111 REV C ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C111 REV C Table 9.2 MII Serial Port Register MAP 73 DATASHEET Revision 1.91 (06-01-09) ...
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... PHY will return a ‘1’ until ANEG is initiated, writing a ‘0’ does not affect the ANEG process. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY ANEG_EN PDN MII_DIS Reserved Reserved Reserved DATASHEET Datasheet ANEG_RST DPLX RW Reserved Reserved The internal PHY SMSC LAN91C111 REV C ...
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... When read as ‘1’ indicate ANEG has been completed and that contents in registers 4,5,6 and 7 are valid. ‘0’ means ANEG has not completed and contents in registers 4,5,6 and 7 are meaningless. The PHY returns zero if ANEG is disabled. SMSC LAN91C111 REV C CAP_TF CAP_TH ...
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... Non-PCI Ethernet Single Chip MAC + PHY DEFAULT VALUE 0000000000010110 111110 000100 - - - - RF Reserved Reserved Reserved Reserved DATASHEET Datasheet R/W SOFT RESET R Retains Original Value R Retains Original Value R Retains Original Value R Retains Original Value Reserved T4 TX_FDX Reserved Reserved CSMA SMSC LAN91C111 REV C ...
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... Only modes supported by the PHY can be set. CSMA A '1' indicates the PHY is capable of 802.3 CSMA Operation 9.5 Register 5. Auto-Negotiation Remote End Capability Register NP ACK TX_HDX 10_FDX 10_HDX The bit definitions are analogous to the Auto Negotiation Advertisement Register. SMSC LAN91C111 REV C Reserved Reserved Reserved Reserved DATASHEET Reserved ...
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... Reserved, Must be 0 for Proper Operation 1 = Bypass Scrambler/Descram bler Bypass 1 = Disable AutoNegotiation with devices that transmit unscrambled idle on powerup and various instances 0 = Enables AutoNegotiation with devices that transmit unscrambled idle on powerup and various instances 1 = Receive Equalizer Disabled, Set To 0 Length SMSC LAN91C111 REV C ...
Page 79
... TLVL0-3 TRF0-1 9.7 Register 17. Configuration 2 - Structure and Bit Definition Reserved Reserved Reserved Reserved Reserved APOLDIS APOLDIS: JABDIS: MREG: SMSC LAN91C111 REV C Select Cable Type Select Receive Input Level Adjust Transmit Output Level Adjust Transmitter Rise/Fall Time Adjust Reserved Reserved JABDIS MREG ...
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... Idle 0 = Interrupt Not Signaled On MDIO ESD RPOL JAB R/LT R/LT R/ Reserved Reserved Reserved Interrupt Bit(s) Have Changed Since Last Read Operation Change 1 = Link Not Detected 0 = Normal 1 = Descrambler Has Lost Synchronization 0 = Normal 1 = Invalid 4B5B Code Detected On Receive Data 0 = Normal SMSC LAN91C111 REV C ...
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... DPLXDET: Reserved: 9.9 Register 19. Mask - Structure and Bit Definition MINT MLNKFAIL MLOSSSYN MSPDDT MDPLDT Reserved MINT: SMSC LAN91C111 REV C Start Of Stream Error End Of Stream Error Reverse Polarity Detect Jabber Detect 100/10 Speed Detect Duplex Detect Reserved MCWRD MSSD Reserved Reserved Interrupt Mask ...
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... No Mask 1 = Mask Interrupt For ESD In Register Mask 1 = Mask Interrupt For RPOL In Register Mask 1 = Mask Interrupt For JAB In Register Mask 1 = Mask Interrupt For SPDDET In Register Mask 1 = Mask Interrupt For DPLXDET In Register Mask Reserved for Factory Use Reserved Reserved Reserved SMSC LAN91C111 REV C ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet Reserved Reserved Reserved Reserved:Reserved for Factory Use SMSC LAN91C111 REV C Reserved Reserved DATASHEET Reserved Reserved Reserved Revision 1.91 (06-01-09) ...
Page 84
... MMU packet numbers are now free. The internal PHY entered in powerdown mode, the TP outputs are in high impedance state. Ethernet MAC gates the RX Clock, TX clock derived from the Internal PHY. The EPH Clock is also disabled. 84 DATASHEET Datasheet and Table 10.2, the SMSC LAN91C111 REV C ...
Page 85
... Packet Number Register into the TX FIFO. The transmission is now enqueued. No further CPU intervention is needed until a transmit interrupt is generated. 5 SMSC LAN91C111 REV C CONTROLLER FUNCTION Ethernet MAC Enables the RX Clock, TX clock derived from the Internal PHY. The EPH Clock is also enabled. The PHY is then set in isolation mode (MII_DIS bit is set). Need to clear this MII_DIS bit ...
Page 86
... TX FIFO PORTS Register. MAC SIDE The enqueued packet will be transferred to the MAC block as a function of TXENA (nTCR) bit and of the deferral process (1/2 duplex mode only) state. Transmit pages are released by transmit completion. 86 DATASHEET Datasheet SMSC LAN91C111 REV C ...
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... When processing is complete the CPU issues the REMOVE AND RELEASE FROM TOP OF RX command to have the MMU free up the used memory and packet number. SMSC LAN91C111 REV C MAC SIDE The MAC generates a TXEMPTY interrupt upon a completion of a sequence of enqueued packets. ...
Page 88
... Figure 10.1 Interrupt Service Routine 88 DATASHEET Datasheet Yes Call RXINTR Write Allocated Pkt # into Packet Number Reg. Write Ad Ptr Reg. & Copy Data & Source Address Enqueue Packet Set "Ready for Packet" Flag Return Buffers to Upper Layer Disable Allocation Interrupt Mask SMSC LAN91C111 REV C ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C111 REV C RX INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM Yes No Destination Multicast? Read Words from RAM for Address Filtering Address No Yes Filtering Pass? No Yes Status Word OK? Do Receive Lookahead ...
Page 90
... Temp = Temp & 0x003F Write (Temp, (Bank2, Offset 2)) // Option 1: Release the packet Write (0x00A0, (Bank2, Offset 0)); //Option 2: Re-Enqueue the packet Write (0x00C0, (Bank2, Offset 0)); Temp = Read(Bank0, Offset 0); Temp = Temp2 OR 0x0001 Write (Temp2, (Bank 0, Offset 0)); Figure 10.3 TX INTR 90 DATASHEET Datasheet SMSC LAN91C111 REV C ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet TXEMPTY = 0 & TXINT = 0 (Waiting for Completion) Figure 10.4 TXEMPTY INTR (Assumes Auto Release Option Selected) SMSC LAN91C111 REV C TXEMPTY INTR Write Acknowledge Reg. with TXEMPTY Bit Set Read TXEMPTY & TX INTR TXEMPTY = 1 TXEMPTY = X & ...
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... Figure 10.5 Drive Send and Allocate Routines MEMORY PARTITIONING Unlike other controllers, the LAN91C111 does not require a fixed memory partitioning between transmit and receive resources. The MMU allocates and de-allocates memory upon different events. An additional mechanism allows the CPU to prevent the receive process from starving the transmit memory allocation ...
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... In this case, the transmit interrupt service routine can find the next packet number to be serviced by reading the TX FIFO PACKET NUMBER at the FIFO PORTS register. This eliminates the need for the driver to keep a list of packet numbers being transmitted. The numbers are queued by the LAN91C111 and provided back to the CPU as their transmission completes. ...
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... M.S. BIT ONLY Figure 10.6 Interrupt Generation for Transmit, Receive, MMU Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 'NOT EMPTY' PACKET NUMBER REGISTER CSMA ADDRESS CPU ADDRESS PACK # OUT 94 DATASHEET Datasheet RX FIFO PACKET NUMBER RX PACKET NUMBER SMSC LAN91C111 REV C ...
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... IOS jumpers. In order to support a software utility based installation, even if the EEPROM was never programmed, the EEPROM can be written using the LAN91C111. One of the IOS combination is associated with a fixed default value for the key parameters (I/O BASE) that can always be used regardless of the EEPROM based value being programmed ...
Page 96
... STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the LAN91C111 can be read or written until the EEPROM operation completes and both bits are clear. This mechanism is also valid for reset initiated reloads. Note EEPROM is connected to the LAN91C111, for example for some embedded applications, the ENEEP pin should be grounded and no accesses to the EEPROM will be attempted ...
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... Non-PCI Ethernet Single Chip MAC + PHY Datasheet IOS2-0 WORD ADDRESS 000 001 010 011 100 101 110 XXX Figure 11 Serial EEPROM Map SMSC LAN91C111 REV C 16 BITS 0h CONFIGURATION REG. 1h BASE REG. 4h CONFIGURATION REG. 5h BASE REG. 8h CONFIGURATION REG. 9h BASE REG. Ch CONFIGURATION REG. ...
Page 98
... EISA 32 bit slave VL Local Bus 32 Bit Systems On VL Local Bus and other 32 bit embedded systems the LAN91C111 is accessed bit peripheral in terms of the bus interface. All registers except the DATA REGISTER will be accessed using byte or word instructions. Accesses to the DATA REGISTER could use byte, word, or dword instructions ...
Page 99
... Table 12.1 VL Local Bus Signal Connections (continued) VL BUS LAN91C111 SIGNAL SIGNAL D0-D31 D0-D31 nLDEV nLDEV VCC nRD nWR GND A1 nVLBUS OPEN nDATCS SMSC LAN91C111 REV C NOTES 32 bit data bus. The bus byte(s) used to access the device are a function of nBE0-nBE3: nBE0 nBE1 nBE2 Double word access ...
Page 100
... Delay 1 LCLK nLRDY nLDEV HIGH-END ISA OR NON-BURST EISA MACHINES On ISA machines, the LAN91C111 is accessed bit peripheral. The signal connections are listed in the following table: Table 12.2 High-End ISA or Non-Burst EISA Machines Signal Connectors ISA BUS LAN91C111 SIGNAL SIGNAL ...
Page 101
... VCC nBE2, nBE3, nCYCLE, W/nR, nRDYRTN, LCLK SMSC LAN91C111 REV C NOTES I/O Write strobe - asynchronous write access. Address is valid before leading edge. Data is latched on trailing edge. This signal is negated on leading nRD, nWR if necessary then asserted on CLK rising edge after the access condition is satisfied. ...
Page 102
... EISA 32 BIT SLAVE On EISA the LAN91C111 is accessed bit I/O slave, along with a Slave DMA type "C" data path option I/O slave, the LAN91C111 uses asynchronous accesses. In creating nRD and nWR inputs, the timing information is externally derived from nCMD edges. Given that the access will be at least 1 ...
Page 103
... Software drivers are not anticipated to generate them. nLDEV is a totem pole output. nLDEV is active on valid decodes of LAN91C111 pins A15-A4, and AEN=0. nNOWS is similar to nLDEV except that it should go inactive on nSTART rising. nNOWS can be used to request compressed cycles (1.5 BCLK long, nRD/nWR will be 1/2 BCLK wide) ...
Page 104
... BCLK nSTART nEX32 Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY NOTES A2-A15 RESET AEN D0-D31 INTR0 LAN91C111 nBE[0:3] nRD nWR LCLK nADS nLDEV O.C. Figure 12.3 LAN91C111 on EISA BUS 104 DATASHEET Datasheet SMSC LAN91C111 REV C ...
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... Schmitt Trigger Hysteresis V I Input Buffer CLK Low Input Level V ILCK High Input Level V IHCK SMSC LAN91C111 REV C 0°C to +70°C for LAN91C111 (-40°C to 85°C for LAN91C111I) -55C° 150°C +325° 0.3V CC -0.3V +5V MIN TYP MAX 0.8 ILI 2 ...
Page 106
... IH I -110 -45 IL +45 +110 IH 0.4 OL 2.4 OH -10 +10 OL 0.4 OL 2.4 OH -10 +10 OL 0.4 OL 2.4 OH -10 +10 OL 0.4 OL 2.4 OH -10 +10 OL 0.4 OL 2.4 OH -10 +10 OL 106 DATASHEET Datasheet UNITS COMMENTS µ µ μ μ µ µ - µ - µ - µ SMSC LAN91C111 REV C ...
Page 107
... Powerdown Supply Current I PDN CAPACITANCE T = 25° 1MHz PARAMETER SYMBOL Clock Input Capacitance Input Capacitance C Output Capacitance C CAPACITIVE LOAD ON OUTPUTS ARDY, D0-D31 (non VLBUS) D0-D31 in VLBUS All other outputs SMSC LAN91C111 REV C MIN TYP MAX 0.4 OL 2.4 OH -10 +10 OL 0.4 OL 2.4 OH -10 +10 ...
Page 108
... Pattern Unscrambled, Measure At 50% Points 100 Mbps, Output Data=scrambled /H/ 100 Mbps 10 Mbps 10 Mbps 10 Mbps, NLP and FLP 10 Mbps. 100 Mbps, UTP with TLVL[3:0]=1000 100 Mbps, STP with TLVL[3:0]=1000 10 Mbps, UTP with TLVL[3:0]=1000 10 Mbps, STP with TLVL[3:0]=1000 SMSC LAN91C111 REV C ...
Page 109
... Threshold RUT TP Input Unsquelch Threshold TP Input Open Circuit Voltage R CMR TP Input Common Mode Voltage Range RDR TP Input Differential Voltage Range RIR TP Input Resistance Input Capacitance SMSC LAN91C111 REV C UNIT TYP MAX 1.2 1.16 +/-50 % 10K Ohm 15 pF LIMIT UNIT MIN TYP MAX ...
Page 110
... High to Data Invalid t5 Data Setup to nWR Inactive t5A Data Hold After nWR Inactive t6 nRD Strobe Width Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY Valid Valid MIN 110 DATASHEET Datasheet t2 t4 Valid t5A TYP MAX UNITS SMSC LAN91C111 REV C ...
Page 111
... High to Data Invalid t5 Data Setup to nWR Inactive t5A Data Hold After nWR Inactive t6 nRD Strobe Width t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising t9 A1-A15, AEN, nBE[3:0] Hold after nADS Rising SMSC LAN91C111 REV C 50ns 100ns 150ns Asynchronous Cycle -- Using nADS t9 valid t8 t3 valid t6 ...
Page 112
... Non-PCI Ethernet Single Chip MAC + PHY 100ns 150ns Asynchronous Cycle - nADS=0 t3A t6A t5 D0~D31 valid Valid Address t26 t26 t13 t26A Valid Figure 14.4 Asynchronous Ready 112 DATASHEET Datasheet 200ns 250n t2 t4 valid t5A MIN TYP MAX UNITS Valid Address Valid Data SMSC LAN91C111 REV C ...
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... W/nR Hold After LCLK Falling t18 Data Setup to LCLK Rising (Write) t20 Data Hold from LCLK Rising (Write) t22 nCYCLE Setup to LCLK Rising t22A nCYCLE Hold After LCLK Rising SMSC LAN91C111 REV C t18 t14 t20 t20 b t15 113 DATASHEET MIN ...
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... W/nR Hold After LCLK Falling t19 Data Delay from LCLK Rising (Read) Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY t12 t14 t19 a b t15 MIN 114 DATASHEET Datasheet t12A t17A t19 c TYP MAX UNITS SMSC LAN91C111 REV C ...
Page 115
... A1-A15, AEN, nBE[3:0] Setup to nADS Rising t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising t25 A4-A15, AEN to nLDEV Delay Clock Address, AEN, nBE[3:0] nADS W/nR nCYCLE Write Data nSRDY Figure 14.8 Synchronous Write Cycle - nVLBUS=0 SMSC LAN91C111 REV Valid t25 MIN TYP 8 5 t10 t9 Valid t8 ...
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... Read Data nSRDY nRDYRTN Figure 14.9 Synchronous Read Cycle - nVLBUS=0 Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY MIN t10 t9 Valid t8 t16 t11 116 DATASHEET Datasheet TYP MAX UNITS t23 t20 t24 Valid t21 t21 SMSC LAN91C111 REV C ...
Page 117
... Hold after LCLK Rising TXD0-TXD3 TXEN100 RXD0-RXD3 RX25 RX_DV RX_ER PARAMETER t27 TXD0-TXD3, TXEN100 Delay from TX25 Rising t28 RXD0-RXD3, RX_DV, RX_ER Setup to RX25 Rising t29 RXD0-RXD3, RX_DV, RX_ER Hold After RX25 Rising SMSC LAN91C111 REV C MIN t27 t27 Figure 14.10 MII Timing MIN ...
Page 118
... DATA t 31 PREAMBLE PREAMBLE DATA t 35 Figure 14.11 Transmit Timing 118 DATASHEET Datasheet UNIT CONDITIONS nS 100Mbps nS 10Mbps nS pk-pk 100Mbps nS pk-pk 10Mbps nS 10Mbps nS 10Mbps mS mS /T/R/ IDLE DATA SOI SMSC LAN91C111 REV C ...
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... Rcv Packet Start to COL Assert Time t39 Xmt Packet Start to COL Assert Time t40 Start of Packet to Transmit JAM Packet Start During JAM t41 Xmt Packet Start to COL Assert Time SMSC LAN91C111 REV C LIMIT UNIT MIN TYP MAX ±3.0 nS pk-pk ±13.5 nS pk-pk 125 ...
Page 120
... Non-PCI Ethernet Single Chip MAC + PHY DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA t 38 Collision Observed by Physical Layer Collision Observed by Physical Layer t 34 Figure 14.13 Collision Timing, Receive 120 DATASHEET Datasheet DATA DATA DATA DATA DATA DATA SMSC LAN91C111 REV C ...
Page 121
... Non-PCI Ethernet Single Chip MAC + PHY Datasheet MII 100 Mbps TPI± I DATA DATA TPO± LEDn MII 10 Mbps TPI± TPO± LEDn SMSC LAN91C111 REV C DATA DATA DATA DATA DATA DATA DATA t 39 Collision Observed by Physical Layer Collision Observed ...
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... Non-PCI Ethernet Single Chip MAC + PHY J K DATA DATA DATA DATA DATA DATA JAM JAM JAM t 41 Collision Observed by Physical Layer t 40 JAM JAM JAM JAM Figure 14.15 Jam Timing 122 DATASHEET Datasheet DATA DATA DATA DATA DATA DATA JAM SMSC LAN91C111 REV C ...
Page 123
... FLP Receive Link Pulse Burst Minimum Period Required For Detection t58 FLP Receive Link Pulse Burst Maximum Period Required For Detection t59 FLP Receive Link Pulses Bursts Required To Detect AutoNegotiation Capability SMSC LAN91C111 REV C LIMIT UNIT MIN TYP MAX See Figure 7.8 nS ...
Page 124
... TPO± TPI± LEDn Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY t 43 a.) Transmit NLP t 46 b.) Receive NLP Figure 14.16 Link Pulse Timing 124 DATASHEET Datasheet t 47 SMSC LAN91C111 REV C ...
Page 125
... CLK TPO± a.) Transmit FLP and Transmit FLP Burst CLK TPI± 31. TPI± LEDn SMSC LAN91C111 REV C DATA CLK t 51 DATA CLK 62.5 93.75 125 t 54 b.) Receive FLP t 58 c.) Receive FLP Burst Figure 14.17 FLP Link Pulse Timing 125 DATASHEET ...
Page 126
... Lead Frame Thickness 0.75 Lead Foot Length from Centerline ~ Lead Length Lead Pitch o 7 Lead Foot Angle 0.23 Lead Width ~ Lead Shoulder Radius 0.20 Lead Foot Radius 0.0762 Coplanarity (Assemblers) 0.08 Coplanarity (Test House) 126 DATASHEET Datasheet SMSC LAN91C111 REV C ...
Page 127
... Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC LAN91C111 REV C MAX REMARKS 3.4 Overall Package Height 0 ...
Page 128
... Fixed commercial temp range to state “0°C to +70°C for LAN91C111” Added bullet: “Commercial Temperature Range from 0°C to 70°C (LAN91C111)” Changed REV default from “0001” to “0010” Changed T1A time in table under figure from 10nS min to 2nS min. ...