LAN91C111I-NS Standard Microsystems (SMSC), LAN91C111I-NS Datasheet

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... TQFP 1.0 mm height lead-free RoHS compliant package Commercial Temperature Range from 0°C to 70°C (LAN91C111) Industrial Temperature Range from -40°C to 85°C (LAN91C111i) Network Interface Fully Integrated IEEE 802.3/802.3u-100Base-TX/ 10Base-T Physical Layer Auto Negotiation: 10/100, Full / Half Duplex On Chip Wave Shaping - No External Filters ...

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... LAN91C111-NS, LAN91C111i-NS (INDUSTRIAL TEMPERATURE) FOR 128-PIN QFP LEAD-FREE ROHS COMPLIANT PACKAGES LAN91C111-NU (1.0MM HEIGHT); LAN91C111i-NU (INDUSTRIAL TEMPERATURE) FOR 128-PIN TQFP LEAD-FREE ROHS COMPLIANT PACKAGES 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2009 SMSC or its subsidiaries. All rights reserved. ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table of Contents Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . ...

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Bank Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 15 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Figures Figure 2.1 Pin Configuration - LAN91C111-FEAST 128 PIN TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet List of Tables Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP and 1.0mm TQFP package Table ...

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Chapter 1 General Description The SMSC LAN91C111 is designed to facilitate the implementation of a third generation of Fast Ethernet connectivity solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design requirements. The LAN91C111 ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 2 Pin Configurations VDD 1 nCSOUT 2 IOS0 3 IOS1 4 IOS2 5 ENEEP 6 EEDO 7 EEDI 8 EESK 9 EECS 10 AVDD 11 RBIAS 12 AGND 13 TPO+ ...

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XTAL1 1 XTAL2 2 3 VDD nCSOUT 4 5 IOS0 IOS1 6 IOS2 7 ENEEP 8 9 EEDO EEDI 10 11 EESK EECS 12 13 AVDD RBIAS 14 AGND 15 TPO+ 16 TPO- 17 AVDD 18 TPI+ 19 TPI- 20 ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 3 Block Diagrams The diagram shown in Figure 3.1, "Basic Functional Block Diagram", describes the device basic functional blocks. The SMSC LAN91C111 is a single chip solution for embedded designs ...

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EEPROM INTERFACE Control Control 8-32 bit Bus Interface Address Control Unit WR FIFO Dynamically Data RD FIFO The diagram shown in Generic Embedded. The Host interface bit wide address / data bus with extensions ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet MII External Signals EEPROM CONTROL TXD[3:0] TX_ER TXEN100 TX25 CRS100 COL100 RXD[3:0] RX_ER RX_DV RX25 MII MDI SERIAL MCLK Manage MDO -ment MII Power PHY AUTONEG On CONTROLS LOGIC Reset Figure ...

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Chapter 4 Signal Descriptions Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP and 1.0mm TQFP package) FUNCTION System Address Bus System Data Bus System Control Bus Serial EEPROM LEDs PHY Crystal Oscillator Power Ground Physical Interface (MII) MISC TOTAL Revision ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 5 Description of Pin Functions PIN NO. NAME TQFP QFP 81-92 83-94 Address 78-80 80-82 Address 41 43 Address Enable 94-97 96-99 nByte Enable 107-104, 109-106, Data Bus 102-99, 76- ...

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PIN NO. NAME TQFP QFP 42 44 Local Bus Clock LCLK 38 40 Asynchronous Ready 43 45 nSynchronous Ready 46 48 nReady Return 29 31 Interrupt 45 47 nLocal Device 31 33 nRead Strobe 32 34 nWrite Strobe 34 36 ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet PIN NO. NAME TQFP QFP 9 11 EEPROM Clock EESK 10 12 EEPROM Select 7 9 EEPROM Data Out 8 10 EEPROM Data In 3-5 5-7 I/O Base 6 8 Enable ...

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PIN NO. NAME TQFP QFP 125 127 Receive Data Valid 112 114 Collision Detect 100 Mbps 113-116 115-118 Transmit Data 109 111 Transmit Clock 118 120 Receive Clock 121-124 123-126 Receive Data 25 27 Management Data Input 26 28 Management ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 6 Signal Description Parameters This section provides a detailed description of each SMSC LAN91C111 signal. The signals are arranged in functional groups according to their associated function. The ‘n’ symbol ...

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Chapter 7 Functional Description 7.1 Clock Generator Block 1. The XTAL1 and XTAL2 pins are to be connected MHz crystal. 2. TX25 is an input clock. It will be the nibble rate of the particular PHY connected ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet 7.4 BIU Block The Bus Interface Unit can handle synchronous as well as asynchronous buses; different signals are used for each one. Transparent latches are added on the address path using ...

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The MAC and external PHY communicate via MDIO and MDC of the MII Management serial interface. MDIO:Management Data input/output. Bi-directional between MAC and PHY that carries management data. All control and status information sent over this pin is driven and ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Figure 7.1 MI Serial Port Frame Timing Diagram SMSC LAN91C111 REV C 23 DATASHEET Revision 1.91 (06-01-09) ...

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MII Packet Data Communication with External PHY The MIl is a nibble wide packet data interface defined in IEEE 802.3. The LAN91C111 meets all the MIl requirements outlined in IEEE 802.3 and shown in TX_EN = 0 IDLE PREAMBLE ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet edges. RXD0 carries the least significant bit and RXD3 the most significant bit of the nibble. RX_DV goes inactive when the last valid nibble of the packet (CRC) is presented at ...

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INTERFRAME GAP PREAMBLE IDLE SSD PREAMBLE PREAMBLE DA, SA, LN, LLC DATA, FCS IDLE PREAMBLE IDLE PREAMBLE DA, SA, LN, LLC DATA, FCS SOI On the transmit side for 100Mbps TX operation, data is received on the controller and then ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet ...

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Table 7.1 4B/5B Symbol Mapping (continued) SYMBOL NAME --- * These 5B codes are not used. For decoder, these 5B codes ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet 7.7.4 Clock and Data Recovery Clock Recovery - 100 Mbps Clock recovery is done with a PLL. If there is no valid data present on the TP inputs, the PLL is ...

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If 25 consecutive descrambled idle pattern 1's are not detected within the 1ms interval, the descrambler goes out of synchronization and restarts the synchronization process. If the descrambler is in the unsynchronized state, the descrambler loss of synchronization detect bit ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet B 1.0 0.8 0.6 0.4 C 0.2 0.0 A -0.2 -0.4 -0.6 -0.8 -1 Figure 7.4 TP Output Voltage Template - 10 MBPS REFERENCE ...

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REFERENCE Transmit Level Adjust The transmit output current level is derived from an internal reference voltage and the external resistor on RBIAS pin. The transmit level can be adjusted with either (1) the ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet STP (150 Ohm) Cable Mode The transmitter can be configured to drive 150 Ohm shielded twisted pair cable. The STP mode can be selected by appropriately setting the cable type select ...

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Figure 7.5 TP Input Voltage Template -10MBPS TP Squelch - 100 Mbps The squelch block determines if the TP input contains valid data. The 100 Mbps TP squelch is one of the criteria used to ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Equalizer Disable The adaptive equalizer can be disabled by setting the equalizer disable bit in the PHY Ml serial port Configuration 1 register. When disabled, the equalizer is forced into the ...

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SSD) is signaled to the controller interface. When False Carrier is detected, the MAC is notified of false carrier and invalid received, and the bad SSD bit is set in the PHY Ml serial port Status Output register. Once a ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet 0 BT 3.1 V 0.5 V/ns 0.25 BT 2.25 BT 585 mV 585 mV sin(2 (t/1BT 0.25 BT and 2.25 t 2.5 BT -3.1 V 2.5 ...

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BT 3.1 V 0.5 V/ns 585 mV 0.5 BT 0.6 BT +50 mV -50 mV 0.25 BT -3.1 V 0.85 BT Figure 7.7 Link Pulse Output Voltage Template - NLP, FLP 100BASE-TX Link Integrity Algorithm -100Mbps Since 100BASE-TX is ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet a.) Normal Link Pulse (NLP) TPO± b.) Fast Link Pulse (FLP) TPO± D0 Clock Clock Data The AutoNegotiation algorithm is initiated by any of these events: (1) AutoNegotiation enabled, (2) a ...

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Link Fail State, and restarts the negotiation process. When AutoNegotiation mode is turned on or reset, software driver should wait for at least 1500ms to read the ANEG_ACK ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Autopolarity Disable The autopolarity feature can be disabled by setting the autopolarity disable bit in the PHY MI serial port Configuration 2 register. 7.7.15 Full Duplex Mode 100 Mbps Full Duplex ...

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R/LT bits are also interrupt bits if they are not masked out with the Mask register bits. Interrupt bits automatically latch themselves into their register locations and assert the interrupt indication when they change state. Interrupt bits stay latched until ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 8 MAC Data Structures and Registers 8.1 Frame Format In Buffer Memory The frame format in memory is similar for the Transmit and Receive areas. The first word is reserved ...

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The receive byte count always appears as even; the ODDFRM bit of the receive status word indicates if the low byte of the last word is relevant. The transmit byte count least significant bit will be assumed 0 by the ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet BROADCAST - Receive frame was broadcast. When a broadcast packet is received, the MULTCAST bit may be also set on the status word in addition to the BRODCAST bit. The software ...

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Regardless of the functional description, all registers can be accessed as doublewords, words or bytes. The default bit values upon hard reset are highlighted below each register. BANK0 0 TCR 2 EPH STATUS 4 RCR 6 COUNTER 8 MIR A ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Bank new register Bank to the SMSC LAN91C111 device. This bank has extended registers that allow the extended feature set of the SMSC LAN91C111. 8.5 Bank 0 - ...

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FORCOL - When set, the FORCOL bit will force a collision by not deferring deliberately. This bit is set and cleared only by the CPU. When TXENA is enabled with no packets in the queue and while the FORCOL bit ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet SQET - Signal Quality Error Test. This bit is set under the following conditions: 1. LAN91C111 is set to operate in Half Duplex mode (SWFDUP=0); 2. When STP_SQET=1 and SWFDUP=0, SQET ...

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ABORT_ENB - Enables abort of receive when collision occurs. Defaults low. When set, the LAN91C111 will automatically abort a packet being received when the appropriate collision input is activated. This bit has no effect if the SWFDUP bit in the ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.9 Bank 0 - Memory Information Register OFFSET MEMORY INFORMATION 8 HIGH BYTE 0 0 LOW BYTE 0 0 FREE MEMORY AVAILABLE - This register can be read at any time ...

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Register) and determine the duplex mode. When this bit is set (1), the Internal PHY will operate at full duplex mode. When this bit is cleared (0), the Internal PHY will operate at half Duplex mode. When the ANEG bit ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet WHAT DO YOU AUTO-NEGOTIATION WANT TO DO? CONTROL BITS 10 Full Duplex Half Duplex LS2A, LS1A, LS0A – LED select Signal Enable. These bits ...

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Reserved – Must be 0. 8.11 Bank 1 - Configuration Register OFFSET 0 The Configuration Register holds bits that define the adapter configuration and are not expected to change during run-time. This register is part of the EEPROM saved setup. ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.12 Bank 1 - Base Address Register OFFSET 2 This register holds the I/O address decode option chosen for the LAN91C111 part of the EEPROM saved setup and is ...

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LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 8.14 Bank 1 - General Purpose Register OFFSET GENERAL PURPOSE A HIGH BYTE 0 0 LOW ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.15 Bank 1 - Control Register OFFSET C CONTROL REGISTER HIGH Reserved RCV_ BYTE BAD 0 0 LOW BYTE LE CR ENABLE ENABLE 0 0 RCV_BAD - When set, bad CRC ...

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Bank 2 - MMU Command Register OFFSET 0 This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control. The three command bits determine the command issued as described below: HIGH ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet OPERATION DECIMAL COMMAND CODE VALUE 110 6 ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting a packet just loaded into RAM. The packet number to ...

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OFFSET ALLOCATION RESULT 3 This register is updated upon an ALLOCATE MEMORY MMU command. FAILED Reserved FAILED - A zero indicates a successful allocation completion. If the allocation fails the bit is set and only cleared when ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet TEMPTY - No transmit packets in completion queue. For polling purposes, uses the TX_INT bit in the Interrupt Status Register. TX FIFO PACKET NUMBER - Packet number presently at the output ...

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Bank 2 - Data Register OFFSET 8 THROUGH DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer register. This register is mapped into two ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet OFFSET C MDINT Reserved OFFSET D MDINT Reserved EPH INT MASK MASK This register can be read and written as a word or as two individual bytes. The ...

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LATCOL - Late Collision 16COL - 16 collisions Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control Register ENABLE (Link Error Enable ENABLE (Counter Roll Over), 3) ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C111 REV C Figure 8.2 Interrupt Structure 65 DATASHEET Revision 1.91 (06-01-09) ...

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Bank 3 - Multicast Table Registers OFFSET 0 THROUG H 7 MULTICAST TABLE LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.23 Bank 3 - Management Interface OFFSET 8 HIGH Reserved MSK_ BYTE CRS100 0 0 LOW Reserved BYTE 0 0 MSK_CRS100 - Disables CRS100 detection during transmit in half duplex mode ...

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Bank 3 - RCV Register OFFSET C HIGH BYTE 0 0 LOW RCV Reserved BYTE DISCRD 0 0 RCV DISCRD - Set to discard a packet being received. Will discard packets only in the process of being received. When ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet CYCLE NCSOUT AEN=0 Driven low. Transparently latched on nADS A3=0 rising edge. A4-15 matches I/O BASE BANK SELECT = 7 BANK SELECT = 4,5,6 High Otherwise High SMSC LAN91C111 REV C ...

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Chapter 9 PHY MII Registers Multiple Register Access Multiple registers can be accessed on a single PHY Ml serial port access cycle with the multiple register access features. The multiple register access features can be enabled by setting the multiple ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet REGISTER ADDRESS PHY Register Description <Idle> <Start> <Read> <Write> IDLE ST[1:0] READ WRITE D[15:0] ↓ Register 0 Control Register 1 Status Register 2 PHY ID#1 Register 3 ...

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SYMBOL NAME DEFINITION REGAD[4:0] Register If REGAD[4:0] = 00000-11110, these bits determine the specific Address register from which D[15:0] is read/written. If multiple register access is enabled and REGAD[4:0] = 11111, all registers are read/written in a single cycle. TA1 ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C111 REV C Table 9.2 MII Serial Port Register MAP 73 DATASHEET Revision 1.91 (06-01-09) ...

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Register 0. Control Register RST LPBK SPEED RW COLST Reserved Reserved RST - Reset A ‘1’ written to this bit will initiate a reset of the PHY. ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet DPLX - Duplex mode When Auto Negotiation is disabled this bit can be used to manually select the link duplex state. Writing a ‘1’ to this bit selects full duplex while ...

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REM_FLT- Remote Fault Detect ‘1’ indicates a Remote Fault. Latches the ‘1’ condition and is cleared by reading this register or resetting the PHY. CAP_ANEG - AutoNegotiation Capable Indicates the ability (‘1’) to perform ANEG or not (‘0’). LINK - ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet NP - Next Page A ‘1’ indicates the PHY wishes to exchange Next Page information. ACK - Acknowledge It is used by the Auto-negotiation function to indicate that a device has ...

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Register 16. Configuration 1- Structure and Bit Definition LNKDIS XMTDIS XMTPDN CABLE RLVL0 TLVL3 LNKDIS: XMTDIS: XMTPDN: RESERVED: BYPSCR: UNSCDS: EQLZR: Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet CABLE RLVL0 TLVL0-3 TRF0-1 9.7 Register 17. Configuration 2 - Structure and Bit Definition Reserved Reserved Reserved Reserved Reserved APOLDIS APOLDIS: ...

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INTMDIO: Reserved: 9.8 Register 18. Status Output - Structure and Bit Definition INT LNKFAIL LOSSSYNC R R/LT R/ SPDDET DPLXDET Reserved R/LT R/ INT: LNKFAIL: LOSSSYNC: CWRD: Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet SSD: ESD: RPOL: JAB: SPDDET: DPLXDET: Reserved: 9.9 Register 19. Mask - Structure and Bit Definition MINT MLNKFAIL MLOSSSYN MSPDDT MDPLDT Reserved ...

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MLNKFAIL: MLOSSSYN: MCWRD: MSSD: MESD: MRPOL: MJAB: MSPDDT: MDPLDT: Reserved: 9.10 Register 20. Reserved - Structure and Bit Definition Reserved Reserved Reserved Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY Interrupt Mask ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Reserved Reserved Reserved Reserved:Reserved for Factory Use SMSC LAN91C111 REV C Reserved Reserved DATASHEET Reserved Reserved Reserved ...

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Chapter 10 Software Driver and Hardware Sequence Flow 10.1 Software Driver and Hardware Sequence Flow for Power Management This section describes the sequence of events and the interaction between the Host Driver and the Ethernet controller to perform power management. ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 10.2 Flow Of Events For Restoring Device In Normal Power Mode S/W DRIVER 1 Write and set (1) the “EPH Power EN” Bit, located in the configuration register, Bank 1 ...

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S/W DRIVER 6 7 SERVICE INTERRUPT - Read Interrupt Status Register transmit interrupt, read the TX FIFO Packet Number from the FIFO Ports Register. Write the packet number into the Packet Number Register. The corresponding status ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet S/W DRIVER 7 8 SERVICE INTERRUPT – Read Interrupt Status Register, exit the interrupt service routine. Option 1) Release the packet. Option 2) Check the transmit status in the EPH STATUS ...

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Call TX INTR or TXEMPTY INTR Get Next TX Packet Available for Transmission? Yes Call ALLOCATE Call EPH INTR Call MDINT Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY ISR Save Bank Select & Address Ptr Registers ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C111 REV C RX INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM Yes No Destination Multicast? Read Words from RAM for Address Filtering Address ...

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TX Interrupt With AUTO_RELEASE = FALSE 1. Save the Packet Number Register Saved_PNR = Read Byte (Bank 2, Offset 2) 2. Read the EPH Status Register Temp = Read (Bank 0, Offset 2) 3. Acknowledge TX Interrupt Write Byte (0x02, ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet TXEMPTY = 0 & TXINT = 0 (Waiting for Completion) Figure 10.4 TXEMPTY INTR (Assumes Auto Release Option Selected) SMSC LAN91C111 REV C TXEMPTY INTR Write Acknowledge Reg. with TXEMPTY Bit ...

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iste ATE E xit D ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet multicast packets that might not be for the node, and that are not subject to upper layer software flow control. INTERRUPT GENERATION The interrupt strategy for the transmit and receive processes ...

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INTERRUPT STATUS REGISTER RCV INT TX EMPTY TWO INT OPTIONS TX INT ALLOC INT 'EMPTY' 'NOT EMPTY' TX DONE PACKET NUMBER M.S. BIT ONLY Figure 10.6 Interrupt Generation for Transmit, Receive, MMU Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 11 Board Setup Information The following parameters are obtained from the EEPROM as board setup information: ETHERNET INDIVIDUAL ADDRESS I/O BASE ADDRESS MII INTERFACE All the above mentioned values are ...

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STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the LAN91C111 can be read or written until the EEPROM operation completes and both bits are clear. This mechanism is also valid for reset ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet IOS2-0 WORD ADDRESS 000 001 010 011 100 101 110 XXX Figure 11 Serial EEPROM Map SMSC LAN91C111 REV C 16 BITS 0h CONFIGURATION REG. 1h BASE REG. ...

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Chapter 12 Application Considerations The LAN91C111 is envisioned to fit a few different bus types. This section describes the basic guidelines, system level implications and sample configurations for the most relevant bus types. All applications are based on buffered architectures ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 12.1 VL Local Bus Signal Connections (continued) VL BUS LAN91C111 SIGNAL SIGNAL D0-D31 D0-D31 nLDEV nLDEV VCC nRD nWR GND A1 nVLBUS OPEN nDATCS SMSC LAN91C111 REV C NOTES 32 ...

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VLBUS W/nR A2-A15 LCLK M/nIO nRESET IRQn D0-D31 nRDYRTN nBE0-nBE3 nADS Delay 1 LCLK nLRDY nLDEV HIGH-END ISA OR NON-BURST EISA MACHINES On ISA machines, the LAN91C111 is accessed bit peripheral. The signal connections are listed in ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 12.2 High-End ISA or Non-Burst EISA Machines Signal Connectors (continued) ISA BUS LAN91C111 SIGNAL SIGNAL nIOWR nWR IOCHRDY ARDY RESET RESET A0 nBE0 nSBHE nBE1 IRQn INTR0 D0-D15 D0-D15 nIOCS16 ...

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ISA BUS A1-A15, AEN RESET VCC D0-D15 IRQ nIORD nIOWR A0 nSBHE nIOCS16 EISA 32 BIT SLAVE On EISA the LAN91C111 is accessed bit I/O slave, along with a Slave DMA type "C" data path option. As ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 12.3 EISA 32 Bit Slave Signal Connections (continued) EISA BUS LAN91C111 SIGNAL SIGNAL Latched W-R nRD combined with nCMD Latched W-R nWR combined with nCMD nSTART nADS RESDRV RESET nBE0 ...

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Table 12.3 EISA 32 Bit Slave Signal Connections (continued) EISA BUS LAN91C111 SIGNAL SIGNAL GND A1 EISA BUS LA2- LA15 RESET AEN M/nIO D0-D31 IRQn nBE[0:3] LATCH nCMD + nWR gates BCLK nSTART nEX32 Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet ...

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... Schmitt Trigger Hysteresis V I Input Buffer CLK Low Input Level V ILCK High Input Level V IHCK SMSC LAN91C111 REV C 0°C to +70°C for LAN91C111 (-40°C to 85°C for LAN91C111I) -55C° 150°C +325° 0.3V CC -0.3V +5V MIN TYP MAX 0.8 ILI 2 ...

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PARAMETER SYMBOL Input Leakage (All I and IS buffers except pins with pullups/pulldowns) Low Input Leakage I High Input Leakage IP Type Buffers Input Current ID Type Buffers Input Current I O4 Type Buffer Low Output Level V High Output ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet PARAMETER SYMBOL I/O24 Type Buffer Low Output Level V High Output Level V Output Leakage I I/OD Type Buffer Low Output Level V High Output Level V Output Leakage I Supply ...

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Twisted Pair Characteristics, Transmit V = 3.3v +/- 5% DD RBIAS = 11K +/- load LIMIT SYM PARAMETER MIN Differential Output 0.950 Voltage 1.165 2.2 2.694 Tovs TP Differential Output 98 Voltage Symmetry ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet LIMIT SYM PARAMETER MIN T OIR TP Output Current 0.80 Adjustment Range 0.86 TORA TP Output Current TLVL Step Accuracy TOR TP Output Resistance Output Capacitance 13.4 Twisted ...

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Chapter 14 Timing Diagrams Address, AEN, nBE[3:0] nADS Read Data nRD, nWR Write Data Figure 14.1 Asynchronous Cycle - nADS=0 PARAMETER t1 A1-A15, AEN, nBE[3:0] Valid to nRD, nWR Active t2 A1-A15, AEN, nBE[3:0] Hold After nRD, nWR Inactive (Assuming ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet 0ns Addr,AEN,nBE[1:0] nADS Read Data nRD,nWR Write Data Figure 14.2 Asynchronous Cycle - Using nADS PARAMETER t1 A1-A15, AEN, nBE[3:0] Valid to nRD, nWR Active t3 nRD Low to Valid Data ...

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Read Data t1A nRD,nWR Write Data Figure 14.3 Asynchronous Cycle - nADS=0 PARAMETER t1A nDATACS Setup to nRD, nWR Active t2 nDATACS Hold After nRD, nWR Inactive (Assuming nADS Tied Low) t3A nRD Low to Valid Data ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet PARAMETER t26 ARDY Low Pulse Width t26A Control Active to ARDY Low t13 Valid Data to ARDY High t12 t17 t22 Clock nDATACS W/nR nCYCLE Write Data a nRDYRTN Figure 14.5 ...

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Clock nDATACS W/nR nCYCLE Read Data nRDYRTN Figure 14.6 Burst Read Cycles - nVLBUS=1 PARAMETER t12 nDATACS Setup to LCLK Rising t12A nDATACS Hold after LCLK Rising t14 nRDYRTN Setup to LCLK Falling t15 nRDYRTN Hold after LCLK Falling ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet nADS Address, AEN, nBE[3:0] nLDEV Figure 14.7 Address Latching for All Modes PARAMETER t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising t25 A4-A15, ...

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PARAMETER t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising t10 nCYCLE Setup to LCLK Rising t11 nCYCLE Hold after LCLK Rising (Non-Burst Mode) t16 W/nR Setup to nCYCLE Active t17A W/nR Hold ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet PARAMETER t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising t10 nCYCLE Setup to LCLK Rising t11 nCYCLE Hold after LCLK Rising (Non-Burst Mode) ...

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AC TEST TIMING CONDITIONS Unless otherwise noted, all test conditions are as follows 3.3V +/- RBIAS = 11K +/- 1%, no load 3. Measurement Points: 4. TPO±, TPI±: 0.0 V During Data, ±0.3V at start/end ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 14.2 Receive Timing Characteristics SYM PARAMETER t36 Receive Input Jitter t37 SOI Pulse Minimum Width Required for Idle Detection t 36 TPI± DATA DATA DATA DATA DATA Figure 14.12 Receive ...

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MII 100 Mbps TPO± I DATA TPI± LEDn MII 10 Mbps TPO± TPI± LEDn Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY DATA DATA DATA DATA DATA DATA DATA DATA DATA ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet MII 100 Mbps TPI± I DATA DATA TPO± LEDn MII 10 Mbps TPI± TPO± LEDn SMSC LAN91C111 REV C DATA DATA DATA DATA DATA DATA ...

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MII 100 Mbps TPO± TPO± MII 10 Mbps TPI± TPO± Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY J K DATA DATA DATA DATA DATA DATA ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 14.4 Link Pulse Timing Characteristics SYM PARAMETER t42 NLP Transmit Link Pulse Width t43 NLP Transmit Link Pulse Period t44 NLP Receive Link Pulse Width Required For Detection t45 NLP ...

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TPO± TPI± LEDn Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY t 43 a.) Transmit NLP t 46 b.) Receive NLP Figure 14.16 Link Pulse Timing 124 DATASHEET Datasheet t 47 ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet CLK DATA CLK TPO± a.) Transmit FLP and Transmit FLP Burst CLK TPI± 31. TPI± ...

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Chapter 15 Package Outlines Figure 15.1 128 Pin TQFP Package Outline, 14X14X1.0 Body Table 15.1 128 Pin TQFP Package Parameters MIN NOMINAL 0. 0.95 1.00 D 15.80 16.00 D/2 7.90 8.00 D1 13.80 14.00 ...

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Non-PCI Ethernet Single Chip MAC + PHY Datasheet Figure 15.2 128 Pin QFP Package Outline, 3.9 MM Footprint Table 15.2 128 Pin QFP Package Parameters MIN NOMINAL 0. 2. 23.70 23.90 ...

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... Table 16.1 Customer Revision History The following ordering information has been removed: “LAN91C111-NC, LAN91C111i-NC (Industrial Temperature) for 128 pin QFP packages”, “LAN91C111-NE, LAN91C111i-NE (Industrial Temperature) for 128-pin TQFP packages” as these has been discontinued. Updated document references to Rev. C. Fixed commercial temp range to state “0°C to +70° ...