JL82571EB Intel, JL82571EB Datasheet - Page 15

• Manufacturer Part Number: JL82571EB
• Manufacturer: Intel

Specifications of JL82571EB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Datasheet—82571/82572 Ethernet Controller
3.4
SMB and Fast Management Link Bus Signals
SMBCLK0/FLBMCK
PCI_PWR_GOOD
SMBD0/FLBMD
SMBALRT_N/
FLBINTEX
Symbol
FLBSD
Type
I/O
I/O
I/O
O
O
SMB Clock
The SMB Clock signals are open drain signals for the serial SMB interface
(Ports A and B). Alternatively, when SMB Port A is configured for a Fast
Management Link Bus, SMB Clock A becomes the Fast Management Link Bus
Master Clock. The Fast Management Link Bus can be clocked up to 6.5 MHz.
Note: Only SMBus 0 is supported; use only SMBCLK0. SMBCLK1 (pin P13) is
reserved. Do not use this pin. Connect it to 3.3 V through a 100K ohm
resistor.
SMB Data
The SMB Data signals are open drain signals for the serial SMB interface
(Ports A and B). Alternatively, when SMB Port A is configured for a Fast
Management Link Bus, SMB Data A becomes Fast Management Link Bus
Master Data.
Note: Only SMBus 0 is supported; use only SMBD0. SMBD1 (pin P12) is
reserved. Do not use this pin. Connect it to 3.3 V through a 100K ohm
resistor.
SMB Alert
The SMB Alert signal is an open drain signal for serial SMB Port A. In ASF
mode, this signal acts as a power good input. It acts as an alert input in
82559 compatible mode.
Fast Management Link Bus Slave Data.
When SMB Port A is configured for a Fast Management Link Bus, this signal
becomes the serial data path for slave data from the 82571EB/82572EI
controller.
Fast Management Link Bus Interrupt Extension
Driven by the 82571EB/82572EI controller as a slave to alert the master to
read data. Alternatively, it signals the master to extend the low phase of the
clock.
Name and Function
11