CPC7593ZC IXYS, CPC7593ZC Datasheet - Page 15

• Manufacturer Part Number: CPC7593ZC
• Manufacturer: IXYS

Specifications of CPC7593ZC

• Lead Free Status / RoHS Status: Supplier Unconfirmed

2. Functional Description
2.1 Introduction
The CPC7593 has the following states:
•
•
•
•
•
•
•
•
See
The CPC7593 offers break-before-make and
make-before-break switching from the ringing state to
the talk state with simple TTL level logic input control.
Solid-state switch construction means no impulse
noise is generated when switching during ringing
cadence or ring trip, eliminating the need for external
zero-cross switching circuitry. State-control is via TTL
logic-level input so no additional driver circuitry is
required. The linear line break switches SW1 and
SW2 have exceptionally low R
matching characteristics. The ringing switch, SW4,
has a minimum open contact breakdown voltage of
465 V at +25°C, sufficiently high with proper protection
to prevent breakdown in the presence of a transient
fault condition (i.e., passing the transient on to the
ringing generator).
Integrated into the CPC7593 is an over-voltage
clamping circuit, active current limiting, and a thermal
shutdown mechanism to provide protection to the
SLIC during a fault condition. Positive and negative
lightning surge currents are reduced by the current
limiting circuitry and hazardous potentials are diverted
away from the SLIC via the protection diode bridge or
the optional integrated protection SCR. Power-cross
potentials are also reduced by the current limiting and
thermal shutdown circuits.
R02
Talk. Loop break switches SW1 and SW2 closed, all
other switches open.
Ringing. Ringing switches SW3 and SW4 closed, all
other switches open.
TESTout. Testout switches SW5 and SW6 closed,
all other switches open.
Ringing generator test. SW7 and SW8 closed, all
other switches open.
TESTin. Testin switches SW9 and SW10 closed, all
other switches open.
Simultaneous TESTin and TESTout. SW9, SW10,
SW5, and SW6 closed, all other switches open.
Simultaneous TESTout and Ringing generator
test. SW5, SW6, SW7, and SW8 closed, all other
switches open (only on the xC and xD versions).
All-Off. All switches open.
“Truth Tables” on page 14
for more information.
ON
and excellent
www.clare.com
To protect the CPC7593 from an overvoltage fault
condition, the use of a secondary protector is required.
The secondary protector must limit the voltage seen at
the T
maximum breakdown voltage of the switches. To
minimize the stress on the solid-state contacts, use of
a foldback or crowbar type secondary protector is
highly recommended. With proper selection of the
secondary protector, a line card using the CPC7593
will meet all relevant ITU, LSSGR, TIA/EIA and IEC
protection requirements.
The CPC7593 operates from a single +5 V supply
only. This gives the device extremely low idle and
active power consumption with virtually any range of
battery voltage. The battery voltage used by the
CPC7593 has a two fold function. For protection
purposes it is used as a fault condition current source
for the internal integrated protection circuitry.
Secondly, it is used as a reference so that in the event
of battery voltage loss, the CPC7593 will enter the
all-off state.
2.2 Under Voltage Switch Lock Out Circuitry
Smart logic in the CPC7593 now provides for switch
state control during both power up and power loss
transitions. An internal detector is used to evaluate the
V
voltage switch lock out circuitry with a rising V
when to assert the under voltage switch lock out
circuitry with a falling V
V
switch control by blocking the information at the
external input pins and conditioning internal switch
commands to the all-off state. Upon restoration of
V
the LATCH input is pulled low.
The rising V
internally set to ensure all internal logic is properly
biased and functional before accepting external switch
commands from the inputs to control the switch states.
For a falling V
assure proper logic and switch behavior up to the
moment the switches are forced off and external
inputs are suppressed.
DD
DD
DD
, the switches will remain in the all-off state until
2.2.1 Introduction
conditions exist, the lock out circuit overrides user
supply to determine when to de-assert the under
LINE
and R
DD
DD
switch lock-out release threshold is
LINE
event, the lock-out threshold is set to
terminals to a level below the
DD
. Any time unsatisfactory low
CPC7593
DD
and
15