DP83932CVF25 National Semiconductor, DP83932CVF25 Datasheet - Page 88

• Manufacturer Part Number: DP83932CVF25
• Manufacturer: National Semiconductor

Specifications of DP83932CVF25

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / RoHS Status: Not Compliant

Number
T56
T60a
T62
T63
T64
T65
T68
T73
T75
T76
T79
T81
T82
T85
T85a
7 0 AC and DC Specifications
REGISTER READ BMODE
Note 1 This figure shows a slave access to the SONIC The BSCK states (T1 T2 etc ) are the equivalent processor states during a slave access
Note 2 If CS is deasserted before the falling edge of SAS T76 T79 and T85 are referenced from the rising edge of CS
Note 3 bcyc
Note 4 It is not necessary to meet the setup time for CS (T56) and the setup time for SAS (T62) since these signals are asynchronously sampled Meeting these
setup times for these signals however makes it possible to use T60a to determine exactly when SMACK will be asserted For multiple register accesses CS can
be held low and SAS can be used to delimit the slave cycle In this case SMACK will be driven low by the SONIC after T60a when T62 is met T85a must be met to
ensure proper slave operation once CS is deasserted
Note 5 The smaller value for T60a refers to when the SONIC is accessed during an Idle condition and the other value refers to when the SONIC is accessed during
non-idle conditions These values are not tested but are guaranteed by design
Note 6 SAS may be asserted low anytime before or simultaneous to the falling edge of CS Register address and slave read write signals are latched on the rising
edge of the SAS and if T62 is met SMACK will be asserted by the SONIC after T60a If T62 is not met SONIC will sample SAS again on the next falling edge of the
clock and SMACK will not be asserted until SAS is deasserted
Note 7 This timing value includes an RC delay inherent in the test measurement These signals typically TRI-STATE 7 ns earlier enabling other devices to drive
these lines without contention
e
bus clock cycle time (T3)
CS Asynch Setup to BSCK (Notes 4 6)
CS and SAS to SMACK Low (Notes 3 5 6)
SAS Asynch Setup to BSCK (Notes 4 6)
Register Address Setup Time to SAS
Register Address Hold Time from SAS
Minimum SAS Low Width (Notes 4 6)
SWR (Read) Hold from SAS
SWR (Read) Setup to SAS
BSCK to RDYo Low
SAS or CS to RDYo High (Note 2)
SAS or CS to SMACK High (Note 2)
BSCK to SMACK Low
BSCK to Register Data Valid
SAS or CS to Data TRI-STATE (Notes 2 7)
Min CS Deassert Time (Note 3)
e
Parameter
0 (Note 1)
(Continued)
88
Min
20
8
0
7
7
8
8
7
1
20 MHz
Max
20
34
18
22
44
34
4
Min
17
7
0
6
6
7
7
6
1
25 MHz
Max
18
32
16
20
42
32
4
Min
15
6
0
5
5
6
6
5
1
33 MHz
Max
TL F 10492 – 88
16
30
14
18
40
30
4
Units
bcyc
bcyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns