PLRXPL-VC-S43-23-N JDS UNIPHASE, PLRXPL-VC-S43-23-N Datasheet - Page 20

no-image

PLRXPL-VC-S43-23-N

Manufacturer Part Number
PLRXPL-VC-S43-23-N
Description
Manufacturer
JDS UNIPHASE
Datasheet

Specifications of PLRXPL-VC-S43-23-N

Number Of Receivers
1
Protocols Supported
IEEE 802.3
Operating Supply Voltage (typ)
3.3V
Operating Temperature Classification
Commercial
Operating Supply Voltage (max)
3.47V
Operating Supply Voltage (min)
3.14V
Pin Count
20
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Lead Free Status / RoHS Status
Supplier Unconfirmed
20
Memory Address
101
102
103
104
105
106
107
108
109
110-7
110-6
110-5
110-4
110-3
110-2
110-1
110-0
111
112-119
120-127
128-247
248-255
Note :
1. During Tx disable, Tx bias and Tx power will not be monitored.
2. Alarm and warning are latched. The flag registers are cleared when the system Reads AND the alarm/warning condition no longer exists.
Diagnostics Data Map
Value
TX Bias LSB (Note 1)
TX Power MSB (Note 1)
TX Power LSB (Note 1)
RX Power MSB
RX Power LSB
Reserved MSB
Reserved LSB
Reserved MSB
Reserved LSB
Tx Disable State
Soft Tx Disable Control
Reserved
Rate Select State
Soft Rate Select Control
Tx Fault State
LOS State
Data Ready State
Reserved
Optional alarm & warning flag bits (Note 2)
Vendor specific
User/Customer EEPROM
Vendor specific
(continued)
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
Comments
Measured TX output power AD values
Measured RX input power AD values
For 1st future definition of digitized analog input
For 2nd future definition of digitized analog input
Digital State of Tx Disable Pin
Writing “1” OR pulling the Tx_Disable pin will disable
the laser
Digital State of Rate Select Pin
Writing to this bit has no effect
Digital State
Digital State
Digital State; “1” until transceiver is ready
Reserved
Refer to SFF-8472 Revision 10.3
JDSU specific
Field writeable EEPROM
Vendor-specific control

Related parts for PLRXPL-VC-S43-23-N