S2068TB Applied Micro Circuits Corporation, S2068TB Datasheet - Page 7

• Manufacturer Part Number: S2068TB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S2068TB

• Number Of Receivers: 2
• Protocols Supported: IEEE 802.3z
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.47V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Not Compliant

The frequency of the reference clock must be either
1/10 the serial data rate, CLKSEL = 0, or 1/20 the
serial data rate, CLKSEL = 1. Note that in both
cases, the frequency of the parallel word rate output,
TCLKO, is constant at 1/10 the serial data rate.
Serial Data Outputs
The S2068 provides LVPECL level serial outputs.
Each high speed output should be provided with a
resistor to VSS (Gnd) near the device. A value of
4.5K
impact on power dissipation. The resistance may be
as low as 450
with no substantive performance improvement.
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable de-
livery of data and TBC to the parallel interface, and
before entering the normal operational state of the
circuit. FIFO initialization is performed upon the de-
assertion of the RESET signal. The TCLKO output will
operate normally even when RESET is asserted and
is available for use as an upstream clock source.
RECEIVER DESCRIPTION
Each receiver channel is designed to implement the
IEEE 802.3z Gigabit Ethernet receiver function
through the physical layer. A block diagram showing
the basic function is provided in Figure 4.
Whenever a signal is present, the receiver attempts
to recover the serial clock from the received data
stream. After acquiring bit synchronization, the
S2068 searches the serial bit stream for the occur-
rence of a K28.5 character on which to perform word
synchronization. Once synchronization on both bit
and word boundaries is achieved, the receiver pro-
vides the word-aligned data on its parallel outputs.
Data Input
A differential input receiver is provided for each
channel of the S2068. Each channel has a loopback
mode in which the serial data from the transmitter
replaces external serial data. The loopback function
for the two channels is controlled by the loopback
enable signal, LPEN.
The high speed serial inputs to the S2068 are inter-
nally biased to VDD-1.3V. This facilities AC-coupling
of the differential inputs and termination with a single
differential termination.
DUAL GIGABIT ETHERNET TRANSCEIVER
October 13, 2000 / Revision D
provides optimal performance with minimum
, but will dissipate additional power
Clock Recovery Function
Clock recovery is provided for each channel of the
S2068. The receiver PLL has been optimized for the
needs of Gigabit Ethernet systems. A simple state
machine in the clock recovery macro decides whether
to acquire lock from the serial data input or from the
reference clock. The decision is based upon the fre-
quency and run length of the serial data inputs.
The run-length requirements insure that the S2068
will respond appropriately and quickly to a loss of
signal. The run-length checker looks for a minimum
of 120 consecutive ones or zeros. The checking is
done in parallel, thus 12 parallel words are exam-
ined.
An off-frequency detection circuit in the S2068 moni-
tors the receiver VCO frequency to insure that the
input signal is at a valid data rate. The data stream
must be within 200 ppm of the appropriate rate for
reliable locking of the CRU to the data stream.
If both the off-frequency test and the run-length test
are satisfied, the CRU will attempt to lock to the
incoming data. Note that if the run length test is sat-
isfied due to noise on the inputs, and no signal is
present, the receiver VCO will maintain frequency
accuracy to within 100 ppm of the target rate as
determined by the REFCLK.
In any transfer of PLL control from the serial data to
the reference clock, the RBC1/0x outputs remain
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.
If at any time, the frequency or run length checks are
violated, the state machine forces the VCO to lock to
the reference clock. This is required to guarantee
that the VCO maintains the correct frequency in the
absence of data.
Reference Clock Input
The reference clock must be provided from a low
jitter clock source. The frequency of the received
data stream (divided by 10 or 20) must be within 200
ppm of the reference clock to insure reliable locking
of the receiver PLL. A single reference clock is pro-
vided to both the transmitter and the receiver of the
S2068.
S2068
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