ST20184 STMicroelectronics, ST20184 Datasheet - Page 2

• Manufacturer Part Number: ST20184
• Manufacturer: STMicroelectronics

Specifications of ST20184

• Main Category: Chipset
• Sub-category: Analog Front End
• Data Rate: 24Mbps
• Transmit Rate Range: 2.5 to 24kbps
• Power Supply Type: Analog
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: TQFP
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Supply Current: 280mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

ST20190
achieved due to a new generation analog front end chip that includes a high resolution ADC/DAC, inte-
grated and programmable filters and low noise/high linearity amplifiers and line driver. Advanced equal-
ization techniques are developed both in the time and frequency domain (PTEQ) and are implemented
both in the analog and digital part of the chipset. In addition, with the introduction of echo cancellation,
digital clock recovery and innovative system algorithms, users recieve best in class performance against
the newest generation DSLAMs.
Figure 2. The ST20190 is available with multi-mode software ranging from ADSL2+ for short loops
to ADSL2 annexL for long loops.
4
The functions performed by each IC are as follows:
4.1 Analog front-end (ST20184) description
Compared to its widely deployed predecessors, the ST20184 has been designed in a shorter gate-length,
advanced analog CMOS technology. Due to the transition in semiconductor technology and the introduc-
tion of advanced design techniques, CAD tools and simulation software, the performance has been opti-
mized to define the next generation requirements.
The ST20184 contains a powerful 5V line driver. In the receiving path great care has been taken to lower
the noise floor, increase the dynamic range and linearity of the programmable gain amplifiers (LNAfs). In
both Rx and Tx path tunable, active filters have been integrated to deal with the different frequency allo-
cations for upstream and downstream bands. The analog/digital conversions are accomplished by a more
than 14bit resolution ADC and DAC.External BOM cost reduction, a 2.5V voltage regulator and dying gasp
comparator are integrated and digital clock recovery or time domain interpolation has been implemented
only requiring a X-tal to be attached to the chip.
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4.2 DMT engine (ST20196) description
The ST20196 is designed in main stream digital CMOS technology. The major building blocks are the
DMT engine including the PMD and TC layer, the ARM. microcontroller and the different interfaces, in-
cluding Utopia levels I&II, Ctrl-E, interfacing to the ST20184 and memory.
The DMT engine is compliant with the new ADSL2+ standards and supports features like diagnostics
mode, enhanced power management (L2), 1 bit constellation, relocatable and modulated pilot, etc. In ad-
2/4
Package : TQFP-100
Supply voltages: 3.3V and 5V
Temperature range: -40°C to 85°C
Typical power consumption 900 mW
Chipset Functions
Splitter &
DFE
Line Driver
V-reg D. Gasp
LNA's
Filters
Filters
ST20184
ADC
DAC
ARM
PMD
DMT Engine
SDRAM
EBI
ST20196
TC
Processor
Network