WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 140

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Note:
Note:
10.2.1.1.17 Packet Buffer ECC Status - PBECCSTS (0x0100C; RW)
10.2.1.1.18 Packet Buffer ECC Error Inject - PBEEI (0x01004; RW)
133
This register sets the on-chip receive and transmit storage allocation size. The
allocation value is read/write for the lower six bits. The division between transmit and
receive is done according to the PBA register.
Programming this register does not automatically re-load or initialize internal packet-
buffer RAM pointers. Software must reset both transmit and receive operation (using
the global device reset CTRL.SWRST bit) after changing this register in order for it to
take effect. The PBS register itself is not reset by assertion of the software reset, but is
only reset upon initial hardware power on.
Programming this register should be aligned with programming the PBA register
hardware operation, if PBA and PBS are not coordinated is not determined.
7:0
15:8
16
17
19:18
31:20
0
1
2
3
15:4
23:16
31:24
Bit
Bit
RC
RC
RW
RW
RO
RO
RW
RW
RW
RW
RO
RW
RW
Type
Type
82577 GbE PHY—Intel
0x0
0x0
0b
0b
0x0
0x0
0b
0b
0b
0b
0x0
0x0
0x0
Reset
Reset
Correctable Error Count (Corr_err_cnt). This counter is incremented every
time a correctable error is detected. The counter stops counting after
reaching 0xFF. Cleared by read.
Uncorrectable Error Count (uncorr_err_cnt). This counter is incremented
every time an uncorrectable error is detected. The counter stops counting
after reaching 0xFF. Cleared by read.
ECC enable.
Stop on First Error (SOFE). When set, the ECC test captures the failing
address into Last Failure Address (LFA).
Reserved. Read as zero.
Last Failure Address (LFA). When Stop on first Error (SOFE) bit is set to 1b,
when there is ECC failure, the LFA register captures the failing address of
the failure.
Inject an error on Tx Buffer on header line. When this bit is set, an error is
injected in the next write cycle to a header line of the Tx buffer. Auto
cleared by hardware when an error is injected if PBECCINJ.ENECCADD is
clear (0b).
Inject an error on Tx Buffer on data line. When this bit is set, an error is
injected in the next write cycle to a data line of the Tx buffer. Auto cleared
by hardware when an error is injected if PBECCINJ.ENECCADD is clear
(0b).
Inject an error on Rx Buffer on header line. When this bit is set, an error is
injected in the next write cycle to a header line of the Rx buffer. Auto
cleared by hardware when an error is injected if PBECCINJ.ENECCADD is
clear (0b).
Inject an error on Rx Buffer on data line. When this bit is set, an error is
injected in the next write cycle to a data line of the Rx buffer. Auto cleared
by hardware when an error is injected if PBECCINJ.ENECCADD is clear
(0b).
Reserved.
Error 1 bit location (value of 0xFF - No error injection on this bit).
Error 2 bit location (value of 0xFF - No error injection on this bit).
®
5 Series Express Chipset MAC Programming Interface
Description
Description