WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 153

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Intel
10.2.1.3.9
Note:
10.2.1.3.10 Receive Descriptor Head Queue - RDH (0x02810; RW)
10.2.1.3.11 Receive Descriptor Tail Queue - RDT (0x02818; RW)
10.2.1.3.12 Interrupt Delay Timer (Packet Timer) - RDTR (0x02820; RW)
®
5 Series Express Chipset MAC Programming Interface—82577 GbE PHY
Receive Descriptor Length Queue- RDLEN (0x02808; RW)
This register sets the number of bytes allocated for descriptors in the circular descriptor
buffer. It must be 128-byte aligned.
The descriptor ring must be equal to or larger than eight descriptors.
This register contains the head pointer for the receive descriptor buffer. The register
points to a 16-byte datum. Hardware controls the pointer. The only time that software
should write to this register is after a reset (hardware reset or CTRL.SWRST) and
before enabling the receive function (RCTL.EN). If software were to write to this
register while the receive function was enabled, the on-chip descriptor buffers might be
invalidated and hardware could be become unstable.
This register contains the tail pointer for the receive descriptor buffer. The register
points to a 16-byte datum. Software writes the tail register to add receive descriptors
for hardware to process.
This register is used to delay interrupt notification for the receive descriptor ring by
coalescing interrupts for multiple received packets. Delaying interrupt notification helps
maximize the number of receive packets serviced by a single interrupt.
6:0
19:7
31:20
15:0
31:16
15:0
31:16
15:0
30:16
31
Bits
Bits
Bits
Bits
RO
RW
RO
RW/V
RO
RW
RO
RW
RO
WO
Type
Type
Type
Type
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0b
Reset
Reset
Reset
Reset
Reserved. Ignore on write. Reads back as 0b.
Descriptor Length (LEN)
Reserved. Reads as 0b. Should be written to 0b for future compatibility.
Receive Descriptor Head (RDH).
Reserved. Should be written with 0b.
Receive Descriptor Tail (RDT).
Reserved. Reads as 0b. Should be written to 0b for future compatibility.
Receive Delay Timer. Receive packet delay timer measured in increments of 1.024
ms.
Reserved. Reads as 0b.
Flush Partial Descriptor Block (FPD), when set to 1b, ignored otherwise. Reads 0b.
Description
Description
Description
Description
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