AM79C874VI AMD (ADVANCED MICRO DEVICES), AM79C874VI Datasheet - Page 11
AM79C874VI
Manufacturer Part Number
AM79C874VI
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.AM79C874VI.pdf
(60 pages)
Specifications of AM79C874VI
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PIN DESCRIPTIONS
The following table describes terms used in the pin de-
scriptions.
Media Connections
TX±
Transmitter Outputs
The TX± pins are the differential transmit output pair.
The TX± pins transmit 10BASE-T or MLT-3 signals de-
pending on the state of the link of the port. If the TX±
pins are not used, they can be left unconnected.
RX±
Receiver Input
The RX± pins are the differential receive input pair. The
RX± pins can receive 10BASE-T or MLT-3 signals de-
pending on the state of the link of the port. If the RX±
pins are not used, they can be connected to each other
with standard resistor termination.
FXT±
FX Transmit
These pins are not connected in 10/100BASE-TX
mode.
When FX_SEL (Pin 44) is pulled low, these pins be-
come the PECL level transmit output for 100BASE-FX.
TEST0/FXR-
Test Output/FX Receive
When BURN_IN (Pin 7) is pulled high, this pin serves
as a test mode output monitor pin.
When FX_SEL (Pin 44) is pulled low, this pin becomes
a PECL level negative receive input for 100BASE-FX.
This pin can be left unconnected when the device is op-
erating in 100BASE-TX or 10BASE-T mode.
TEST1/FXR+
Test Output/FX Receive
When BURN_IN (Pin 7) is pulled high, this pin serves
as a test mode output monitor pin.
22235K
Input
Analog Input
Output
Analog Output
High Impedance
Pull-Up
Pull-Down
Term
Table 3. Pin Description Terminology
Digital input to the PHY
Analog input to the PHY
Digital output from the PHY
Analog output from the PHY
Tri-state capable output from the PHY
PHY has internal pull-up resistor.
NC=HIGH
PHY has internal pull-down resistor.
NC=LOW
Description
+Analog Output/Input
-Analog Output/Input
Analog Output
Analog Output
D A T A
Analog Input
S H E E T
Am79C874
When FX_SEL (Pin 44) is pulled low, this pin becomes
a PECL level positive receive input for 100BASE-FX.
This pin can be left unconnected when the device is op-
erating in 100BASE-TX or 10BASE-T mode.
TEST3/SDI+
FX Transceiver Signal Detect Analog Output/Input
When BURN_IN (Pin 7) is pulled high, this pin serves
as a test mode output monitor pin.
This pin is not connected in 10/100BASE-TX mode.
When FX_SEL (Pin 44) is pulled low, this pin becomes
the Signal Detect input from the Fiber-Optic trans-
ceiver. When the signal quality is good, the SDI+ pin
should be driven high.
MII/7-Wire (GPSI) Signals
RXD[3:0]
MII Receive Data
The data is synchronous with RX_CLK when RX_DV is
active. When the 7-wire 10BASE-T interface operation
is enabled (GPIO[0]= HIGH), RXD[0] will serve as the
10 MHz serial data output.
RX_DV
Receive Data Valid
RX_DV is asserted when the NetPHY-1LP device is
presenting recovered nibbles on RXD[3:0]. This in-
cludes the preamble through the last nibble of the data
stream on RXD[3:0]. In 100BASE-X mode, the /J/K/ is
considered part of the preamble; thus RX_DV is as-
serted when /J/K/ is detected. In 10BASE-T mode,
RX_DV is asserted (and data is presented on
RXD[3:0]) when the device detects valid preamble bits.
RX_DV is synchronized to RX_CLK.
RX_CLK/10RXCLK
Receive Clock
A continuous clock (which is active while LINK is estab-
lished) provides the timing reference for RX_DV,
RX_ER, and RXD[3:0] signals. It is 25 MHz in
100BASE-TX/FX and 2.5 MHz in 10BASE-T. To further
reduce power consumption of the overall system, the
device provides an optional mode enabled through MII
Register 16, bit 0 in which RX_CLK is held inactive
(low) when no data is received. If RX_CLK is needed
when LINK is not established, the NetPHY-1LP must
be placed into digital loopback or force the link via reg-
ister 21, bits 13 or 14.
When 7-wire 10BASE-T mode is enabled, this pin will
provide a 10 MHz clock. RX_CLK is high impedance
when the ISO pin is enabled
RX_ER/RXD[4]
Receive Error
When RX_ER is active high, it indicates an error has
been detected during frame reception.
Output, High Impedance
Output, High Impedance
Output, High Impedance
Output, High Impedance
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