DP83847ALQA56AX/HALF National Semiconductor, DP83847ALQA56AX/HALF Datasheet - Page 26

• Manufacturer Part Number: DP83847ALQA56AX/HALF
• Manufacturer: National Semiconductor

Specifications of DP83847ALQA56AX/HALF

• Lead Free Status / RoHS Status: Compliant

3.7 Crystal Oscillator Circuit
The DsPHYTER II supports an external CMOS level oscil-
lator source or a crystal resonator device. If an external
clock source is used, X1 should be tied to the clock source
and X2 should be left floating. In either case, the clock
source must be a 25 MHz 0.005% (50 PPM) CMOS oscilla-
tor or a 25 MHz (50 PPM), parallel, 20 pF load crystal reso-
nator. Figure 10 below shows a typical connection for a
crystal resonator circuit. The load capacitor values will vary
with the crystal vendors; check with the vendor for the rec-
ommended loads.
The oscillator circuit was designed to drive a parallel reso-
nance AT cut crystal with a minimum drive level of 500 W
and a maximum of 1mW. If a crystal is specified for a lower
drive level, a current limiting resistor should be placed in
series between X2 and the crystal.
As a starting point for evaluating an oscillator circuit, if the
requirements for the crystal are not known, C
should be set at 22 pF, and R
4.0 Reset Operation
The DP83847 can be reset either by hardware or software.
A hardware reset may be accomplished by asserting the
RESET pin after powering up the device (this is required)
or during normal operation when a reset is needed. A soft-
ware reset is accomplished by setting the reset bit in the
Basic Mode Control register.
While either the hardware or software reset can be imple-
mented at any time after device initialization, a hardware
reset, as described in Section 4.1 must be provided upon
device power-up/initialization. Omitting the hardware reset
operation
sequence can result in improper device operation.
4.1 Hardware Reset
A hardware reset is accomplished by applying a low pulse
(TTL level), with a duration of at least 160
Figure 10. Crystal Oscillator Circuit
C
during
L1
X1
the
device
1
should be set at 0
power-up/initialization
X2
R
C
1
L2
L1
s, to the
and C
L2
26
3.8 Reference Bypass Couple
To ensure correct operation for the DP83847, parallel caps
with values of 10 F (Tantalum preferred) and .1 F should
be placed close to pin 42 (C1) of the device. See Figure 11
below for proper use of caps.
RESET pin during normal operation. This will reset the
device such that all registers will be reset to default values
and the hardware configuration values will be re-latched
into the device (similar to the power-up/reset operation).
4.2 Software Reset
A software reset is accomplished by setting the reset bit
(bit 15) of the Basic Mode Control Register (BMCR). The
period from the point in time when the reset bit is set to the
point in time when software reset has concluded is approx-
imately 160 s.
The software reset will reset the device such that all regis-
ters will be reset to default values and the hardware config-
uration values will be re-latched into the device (similar to
the power-up/reset operation). Software driver code should
wait 500 s following a software reset before allowing fur-
ther serial MII operations with the DP83847.
Pin 42 (C1)
Figure 11. Reference Bypass Couple
10 F
.1 F
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