DP83847ALQA56AX/HALF National Semiconductor, DP83847ALQA56AX/HALF Datasheet - Page 6

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DP83847ALQA56AX/HALF

Manufacturer Part Number
DP83847ALQA56AX/HALF
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of DP83847ALQA56AX/HALF

Lead Free Status / RoHS Status
Compliant
1.2 10 Mb/s and 100 Mb/s PMD Interface
RXD[3]
RXD[2]
RXD[1]
RXD[0]
RX_ER/PAUSE_EN
RX_DV
TD+, TD-
RD-, RD+
Signal Name
Signal Name
O, PU/PD 26, 27, 29,
S, O, PU
Type
Type
O
O
I
LLP Pin #
LLP Pin #
10, 11
6, 7
30
33
31
RECEIVE DATA: Nibble wide receive data (synchronous to cor-
responding RX_CLK, 25 MHz for 100BASE-TX mode, 2.5 MHz
for 10BASE-T nibble mode). Data is driven on the falling edge of
RX_CLK. RXD[2] has an internal pull-down resistor. The remain-
ing RXD pins have pull-ups.
RECEIVE ERROR: Asserted high to indicate that an invalid sym-
bol has been detected within a received packet in 100BASE-TX
mode.
RECEIVE DATA VALID: Asserted high to indicate that valid data
is present on the corresponding RXD[3:0] for nibble mode. Data
is driven on the falling edge of the corresponding RX_CLK.
Differential common driver transmit output. These differential out-
puts are configurable to either 10BASE-T or 100BASE-TX signal-
ing.
The DP83847 will automatically configure the common driver out-
puts for the proper signal type as a result of either forced config-
uration or Auto-Negotiation.
Differential receive input. These differential inputs can be config-
ured to accept either 100BASE-TX or 10BASE-T signaling.
The DP83847 will automatically configure the receive inputs to
accept the proper signal type as a result of either forced configu-
ration or Auto-Negotiation.
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Description
Description
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