HBLXT9785HC.A4 Intel, HBLXT9785HC.A4 Datasheet - Page 181

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HBLXT9785HC.A4

Manufacturer Part Number
HBLXT9785HC.A4
Description
Manufacturer
Intel
Datasheet

Specifications of HBLXT9785HC.A4

Lead Free Status / RoHS Status
Not Compliant
Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Figure 42. SMII - 100BASE-FX Transmit Timing
Table 63. SMII - 100BASE-FX Transmit Timing Parameters
SYNC setup to REFCLK rising edge and
TxData setup to REFCLK rising edge
SYNC hold from REFCLK rising edge
and TxData hold from REFCLK rising
edge
TxEN sampled to start of /J/
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
testing.
100BASE-TX or 100BASE-FX).
default configuration of 00 (32 bits of initial fill).
REFCLK
TxData
SYNC
TPFO
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Parameter
t
1
t
2
Sym
t
3
t1
t2
t3
Min
1.5
1.0
Typ
10
1
t
1
t
2
Max
17
Units
BT
ns
ns
2
Test Conditions
181

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