SLXT973QCA3V 856775 Intel, SLXT973QCA3V 856775 Datasheet - Page 70
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SLXT973QCA3V 856775
Manufacturer Part Number
SLXT973QCA3V 856775
Description
Manufacturer
Intel
Datasheet
1.SLXT973QCA3V_856775.pdf
(88 pages)
Specifications of SLXT973QCA3V 856775
Lead Free Status / RoHS Status
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LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
70
Table 27. Special Function Register (Address 27)
27.15:13
27.11:10
1. Refer to
2. Register bits 27.11:10 are latched in from hardware pins on hardware reset.
27.3:0
27.12
27.9
27.8
27.7
27.6
27.5
27.4
Bit
Line Length
Indicator
Reserved
Per-Port Rise
time Control
Auto MDIX enable
Auto MDIX
Analog Loopback
Loopback Detect
Enable
Loopback Speed-
Up Enable
Loopback
Detected
Reserved
Table 16 on page 61
Name
111 = Longest
110 =
101 =
100 =
011 =
010 =
001 =
000 = Shortest
Write as 0, ignore on read
00 = 3.3 ns (default pins TxSLEW<1:0>)
01 = 3.6 ns
10 = 3.9 ns
11 = 4.2 ns
0 = Disable Auto-MDIX
1 = Enable Auto-MDIX
MDI/MDIX selection
1 = Enable Analog Loopback (transmits on twisted-
pair)
0 = Disable Analog Loopback
1 = Enable automatic loopback detection.
0 = Disable automatic loopback detection
1 = Enable automatic loopback detection speed-up
0 = Disable automatic loopback detection speed-up
1 = Loopback detected
0 = No loopback detected
Write as 0, ignore on read
0 = MDI, transmit on pair A and receive on pair B
1 = MDIX, transmit on pair B and receive on pair A
for Register Bit Descriptions.
Line Length Indication
Special Functions
Description
Approximate line-
length
corresponding to
each value will be
determined at
design verification
(Not valid when
agcset (Register
bit 30.13 = 1)
Type
Rev. Date: March 1, 2002
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
Document #: 249426
1
Revision #: 002
Datasheet
Default
Note 2
LHR
000
00
0
1
1
0
0
0
0
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