EGLXT973QEA3V Intel, EGLXT973QEA3V Datasheet - Page 11

• Manufacturer Part Number: EGLXT973QEA3V
• Manufacturer: Intel

Specifications of EGLXT973QEA3V

• Lead Free Status / RoHS Status: Compliant

LXT973 PHY Transceiver
Specification Update
249737, Revision 10.0
20 March 2007
Item 4:
Problem
Implication
Workaround None.
Status
Item 5:
Problem
Implication
Workaround To select 100 Mbps operation in fiber mode, tie the SD_2P5V/SPEEDn configuration pins
Status
Item 6:
Problem
Implication
Status
Cortina Systems
MDIO Interface and Repeated Polling
Repeated polling of odd-numbered registers via the MDIO interface randomly returns the
contents of the previous even register.
Managed applications may not obtain the correct register contents when a particular
register is monitored for device status.
This erratum has been previously fixed.
3.3 V Fiber Speed Selection
In fiber mode, the hardware configuration pins (SD_2P5V/SPEEDn) set the speed rather
than set the signal detect voltage threshold.
Setting the SD_2P5V/SPEEDn to Low sets the device in 10 Mbps operation, which is not
supported in fiber mode. The signal detect function defaults to 2.5 V PECL thresholds.
The signal detect input is unreliable when driven from a 3.3 V PECL source.
High through a 10 KΩ resistor to VCC.
To properly terminate the signal detect input, tie the SDn pins High through a 10 KΩ
resistor.
There is no workaround to enable the SD function when using a 3.3 V optical module.
This erratum has been previously fixed.
Far-End Fault Reporting
If a link partner continuously sends successive Far-End Fault (FEF) codes (three sets of
84 1s followed by a 0), the LXT973 PHY Transceiver sets the Remote Fault bit High
(Register bit 1.4 = 1) and drops link (Register bit 1.2 = 0). Register bit 1.4 is cleared after a
Read and is not set High again while the Far-End Fault signal is present.
If the MAC reads Register bit 1.4 more than once under a continuous Far-End Fault
condition, a Far-End Fault is not indicated after the first read.
Once a remote fault has been indicated by Register bit 1.4 = 1, the following sequence
can be used to monitor the remote-fault status.
Managed Systems:
This erratum has been previously fixed.
®
• Write Register 0 = 0x6100: Forces the port to 100 Mbps full-duplex internal loopback,
• Wait: Approximately 100 mS.
• Write Register 0 = 0x2100: Forces the port into 100 Mbps full-duplex. If Far-End Fault
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
link is up, Register bit 1.2 = 1 and Register bit 1.4 = 0.
is present, Register bit 1.4 = 1 indicates Far-End Fault and Register bit 1.2 = 0
indicates link is down.
5.0 Errata
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